mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-15 01:03:24 +09:00
36d0a42b68
Write the TSCR register via 32bit write instead of 16bit one. The register is 32bit wide and bit 16 is being set, triggering gcc overflow error and making the code broken. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel <zpxu@ingenic.cn> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
153 lines
3.9 KiB
C
153 lines
3.9 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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* (C) Copyright 2011
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* Xiangfu Liu <xiangfu@openmobilefree.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/mipsregs.h>
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#include <asm/cacheops.h>
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#include <asm/reboot.h>
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#include <asm/io.h>
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#include <asm/jz4740.h>
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#define cache_op(op, addr) \
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__asm__ __volatile__( \
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".set push\n" \
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".set noreorder\n" \
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".set mips3\n" \
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"cache %0, %1\n" \
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".set pop\n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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void __attribute__((weak)) _machine_restart(void)
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{
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struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
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struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
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u16 tmp;
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/* wdt_select_extalclk() */
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tmp = readw(&wdt->tcsr);
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tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN);
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tmp |= WDT_TCSR_EXT_EN;
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writew(tmp, &wdt->tcsr);
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/* wdt_select_clk_div64() */
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tmp = readw(&wdt->tcsr);
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tmp &= ~WDT_TCSR_PRESCALE_MASK;
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tmp |= WDT_TCSR_PRESCALE64,
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writew(tmp, &wdt->tcsr);
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writew(100, &wdt->tdr); /* wdt_set_data(100) */
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writew(0, &wdt->tcnt); /* wdt_set_count(0); */
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writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
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writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
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while (1)
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;
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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_machine_restart();
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fprintf(stderr, "*** reset failed ***\n");
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return 0;
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}
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
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for (; addr <= aend; addr += lsize) {
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cache_op(Hit_Writeback_Inv_D, addr);
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cache_op(Hit_Invalidate_I, addr);
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}
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}
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void flush_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (stop - 1) & ~(lsize - 1);
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for (; addr <= aend; addr += lsize)
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cache_op(Hit_Writeback_Inv_D, addr);
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}
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (stop - 1) & ~(lsize - 1);
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for (; addr <= aend; addr += lsize)
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cache_op(Hit_Invalidate_D, addr);
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}
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void flush_icache_all(void)
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{
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u32 addr, t = 0;
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__asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */
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__asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */
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for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
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addr += CONFIG_SYS_CACHELINE_SIZE) {
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cache_op(Index_Store_Tag_I, addr);
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}
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/* invalidate btb */
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__asm__ __volatile__(
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".set mips32\n\t"
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"mfc0 %0, $16, 7\n\t"
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"nop\n\t"
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"ori %0,2\n\t"
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"mtc0 %0, $16, 7\n\t"
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".set mips2\n\t"
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:
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: "r" (t));
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}
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void flush_dcache_all(void)
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{
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u32 addr;
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for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
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addr += CONFIG_SYS_CACHELINE_SIZE) {
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cache_op(Index_Writeback_Inv_D, addr);
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}
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__asm__ __volatile__("sync");
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}
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void flush_cache_all(void)
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{
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flush_dcache_all();
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flush_icache_all();
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}
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