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https://github.com/brain-hackers/u-boot-brain
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![Igor Opaniuk](/assets/img/avatar_default.png)
This adds initial minimal support for the Toradex Verdin iMX8M Mini Quad 2GB WB IT V1.0A module. They are now strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U-Boot supports booting from the on-module eMMC only, SDP support is disabled for now due to missing i.MX 8M Mini USB support. Functionality wise the following is known to be working: - eMMC, 8-bit and 4-bit MMC/SD card slots - Ethernet - GPIOs - I2C Boot sequence is: SPL ---> ATF (TF-A) ---> U-boot proper ATF, U-boot proper and u-boot.dtb images are packed into a FIT image, loaded by SPL. Boot: U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100) Normal Boot Trying to boot from MMC1 NOTICE: Configuring TZASC380 NOTICE: RDC off NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty NOTICE: BL31: Built : 01:11:41, Jan 25 2020 NOTICE: sip svc init U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100) CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz Reset cause: POR DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial# 06535149 Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 Verdin iMX8MM # Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
181 lines
3.6 KiB
C
181 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 Toradex
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mm_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <cpu_func.h>
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#include <dm/device.h>
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#include <dm/device-internal.h>
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#include <dm/uclass.h>
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#include <dm/uclass-internal.h>
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#include <hang.h>
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#include <power/bd71837.h>
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#include <power/pmic.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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switch (boot_dev_spl) {
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case MMC1_BOOT:
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return BOOT_DEVICE_MMC1;
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case SD2_BOOT:
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case MMC2_BOOT:
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return BOOT_DEVICE_MMC2;
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case SD3_BOOT:
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case MMC3_BOOT:
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return BOOT_DEVICE_MMC1;
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case USB_BOOT:
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return BOOT_DEVICE_BOARD;
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default:
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return BOOT_DEVICE_NONE;
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}
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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void spl_board_init(void)
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{
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/* Serial download mode */
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if (is_usb_boot()) {
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puts("Back to ROM, SDP\n");
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restore_boot_params();
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}
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puts("Normal Boot\n");
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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/* Verdin UART_3, Console/Debug UART */
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static iomux_v3_cfg_t const uart_pads[] = {
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IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_pads[] = {
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IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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return 0;
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}
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret;
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ret = pmic_get("pmic@4b", &dev);
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if (ret == -ENODEV) {
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puts("No pmic\n");
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return 0;
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}
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if (ret != 0)
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return ret;
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/* decrease RESET key long push time from the default 10s to 10ms */
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pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
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/* unlock the PMIC regs */
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pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
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/* increase VDD_SOC to typical value 0.85v before first DRAM access */
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pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
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/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
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pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
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#ifndef CONFIG_IMX8M_LPDDR4
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/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
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pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
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#endif
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/* lock the PMIC regs */
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pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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arch_cpu_init();
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init_uart_clk(0);
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board_early_init_f();
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timer_init();
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preloader_console_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device_by_name(UCLASS_CLK,
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"clock-controller@30380000",
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&dev);
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if (ret < 0) {
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printf("Failed to find clock node. Check device tree\n");
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hang();
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}
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enable_tzc380();
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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board_init_r(NULL, 0);
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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puts("resetting ...\n");
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reset_cpu(WDOG1_BASE_ADDR);
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return 0;
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}
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