mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
208 lines
5.7 KiB
C
208 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*****************************************************************************
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* (C) Copyright 2003; Tundra Semiconductor Corp.
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* (C) Copyright 2006; Freescale Semiconductor Corp.
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*****************************************************************************/
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/*
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* FILENAME: tsi108.h
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*
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* Originator: Alex Bounine
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*
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* DESCRIPTION:
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* Common definitions for the Tundra Tsi108 bridge chip
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*
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*/
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#ifndef _TSI108_H_
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#define _TSI108_H_
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#define TSI108_HLP_REG_OFFSET (0x0000)
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#define TSI108_PCI_REG_OFFSET (0x1000)
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#define TSI108_CLK_REG_OFFSET (0x2000)
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#define TSI108_PB_REG_OFFSET (0x3000)
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#define TSI108_SD_REG_OFFSET (0x4000)
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#define TSI108_MPIC_REG_OFFSET (0x7400)
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#define PB_ID (0x000)
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#define PB_RSR (0x004)
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#define PB_BUS_MS_SELECT (0x008)
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#define PB_ISR (0x00C)
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#define PB_ARB_CTRL (0x018)
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#define PB_PVT_CTRL2 (0x034)
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#define PB_SCR (0x400)
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#define PB_ERRCS (0x404)
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#define PB_AERR (0x408)
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#define PB_REG_BAR (0x410)
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#define PB_OCN_BAR1 (0x414)
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#define PB_OCN_BAR2 (0x418)
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#define PB_SDRAM_BAR1 (0x41C)
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#define PB_SDRAM_BAR2 (0x420)
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#define PB_MCR (0xC00)
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#define PB_MCMD (0xC04)
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#define HLP_B0_ADDR (0x000)
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#define HLP_B1_ADDR (0x010)
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#define HLP_B2_ADDR (0x020)
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#define HLP_B3_ADDR (0x030)
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#define HLP_B0_MASK (0x004)
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#define HLP_B1_MASK (0x014)
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#define HLP_B2_MASK (0x024)
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#define HLP_B3_MASK (0x034)
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#define HLP_B0_CTRL0 (0x008)
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#define HLP_B1_CTRL0 (0x018)
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#define HLP_B2_CTRL0 (0x028)
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#define HLP_B3_CTRL0 (0x038)
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#define HLP_B0_CTRL1 (0x00C)
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#define HLP_B1_CTRL1 (0x01C)
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#define HLP_B2_CTRL1 (0x02C)
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#define HLP_B3_CTRL1 (0x03C)
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#define PCI_CSR (0x004)
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#define PCI_P2O_BAR0 (0x010)
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#define PCI_P2O_BAR0_UPPER (0x014)
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#define PCI_P2O_BAR2 (0x018)
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#define PCI_P2O_BAR2_UPPER (0x01C)
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#define PCI_P2O_BAR3 (0x020)
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#define PCI_P2O_BAR3_UPPER (0x024)
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#define PCI_MISC_CSR (0x040)
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#define PCI_P2O_PAGE_SIZES (0x04C)
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#define PCI_PCIX_STAT (0x0F4)
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#define PCI_IRP_STAT (0x184)
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#define PCI_PFAB_BAR0 (0x204)
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#define PCI_PFAB_BAR0_UPPER (0x208)
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#define PCI_PFAB_IO (0x20C)
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#define PCI_PFAB_IO_UPPER (0x210)
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#define PCI_PFAB_MEM32 (0x214)
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#define PCI_PFAB_MEM32_REMAP (0x218)
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#define PCI_PFAB_MEM32_MASK (0x21C)
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#define CG_PLL0_CTRL0 (0x210)
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#define CG_PLL0_CTRL1 (0x214)
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#define CG_PLL1_CTRL0 (0x220)
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#define CG_PLL1_CTRL1 (0x224)
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#define CG_PWRUP_STATUS (0x234)
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#define MPIC_CSR(n) (0x30C + (n * 0x40))
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#define SD_CTRL (0x000)
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#define SD_STATUS (0x004)
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#define SD_TIMING (0x008)
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#define SD_REFRESH (0x00C)
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#define SD_INT_STATUS (0x010)
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#define SD_INT_ENABLE (0x014)
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#define SD_INT_SET (0x018)
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#define SD_D0_CTRL (0x020)
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#define SD_D1_CTRL (0x024)
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#define SD_D0_BAR (0x028)
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#define SD_D1_BAR (0x02C)
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#define SD_ECC_CTRL (0x040)
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#define SD_DLL_STATUS (0x250)
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#define TS_SD_CTRL_ENABLE (1 << 31)
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#define PB_ERRCS_ES (1 << 1)
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#define PB_ISR_PBS_RD_ERR (1 << 8)
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#define PCI_IRP_STAT_P_CSR (1 << 23)
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/*
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* I2C : Register address offset definitions
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*/
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#define I2C_CNTRL1 (0x00000000)
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#define I2C_CNTRL2 (0x00000004)
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#define I2C_RD_DATA (0x00000008)
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#define I2C_TX_DATA (0x0000000c)
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/*
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* I2C : Register Bit Masks and Reset Values
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* definitions for every register
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*/
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/* I2C_CNTRL1 : Reset Value */
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#define I2C_CNTRL1_RESET_VALUE (0x0000000a)
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/* I2C_CNTRL1 : Register Bits Masks Definitions */
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#define I2C_CNTRL1_DEVCODE (0x0000000f)
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#define I2C_CNTRL1_PAGE (0x00000700)
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#define I2C_CNTRL1_BYTADDR (0x00ff0000)
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#define I2C_CNTRL1_I2CWRITE (0x01000000)
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/* I2C_CNTRL1 : Read/Write Bit Mask Definition */
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#define I2C_CNTRL1_RWMASK (0x01ff070f)
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/* I2C_CNTRL1 : Unused/Reserved bits Definition */
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#define I2C_CNTRL1_RESERVED (0xfe00f8f0)
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/* I2C_CNTRL2 : Reset Value */
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#define I2C_CNTRL2_RESET_VALUE (0x00000000)
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/* I2C_CNTRL2 : Register Bits Masks Definitions */
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#define I2C_CNTRL2_SIZE (0x00000003)
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#define I2C_CNTRL2_LANE (0x0000000c)
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#define I2C_CNTRL2_MULTIBYTE (0x00000010)
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#define I2C_CNTRL2_START (0x00000100)
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#define I2C_CNTRL2_WR_STATUS (0x00010000)
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#define I2C_CNTRL2_RD_STATUS (0x00020000)
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#define I2C_CNTRL2_I2C_TO_ERR (0x04000000)
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#define I2C_CNTRL2_I2C_CFGERR (0x08000000)
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#define I2C_CNTRL2_I2C_CMPLT (0x10000000)
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/* I2C_CNTRL2 : Read/Write Bit Mask Definition */
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#define I2C_CNTRL2_RWMASK (0x0000011f)
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/* I2C_CNTRL2 : Unused/Reserved bits Definition */
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#define I2C_CNTRL2_RESERVED (0xe3fcfee0)
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/* I2C_RD_DATA : Reset Value */
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#define I2C_RD_DATA_RESET_VALUE (0x00000000)
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/* I2C_RD_DATA : Register Bits Masks Definitions */
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#define I2C_RD_DATA_RBYTE0 (0x000000ff)
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#define I2C_RD_DATA_RBYTE1 (0x0000ff00)
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#define I2C_RD_DATA_RBYTE2 (0x00ff0000)
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#define I2C_RD_DATA_RBYTE3 (0xff000000)
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/* I2C_RD_DATA : Read/Write Bit Mask Definition */
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#define I2C_RD_DATA_RWMASK (0x00000000)
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/* I2C_RD_DATA : Unused/Reserved bits Definition */
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#define I2C_RD_DATA_RESERVED (0x00000000)
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/* I2C_TX_DATA : Reset Value */
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#define I2C_TX_DATA_RESET_VALUE (0x00000000)
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/* I2C_TX_DATA : Register Bits Masks Definitions */
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#define I2C_TX_DATA_TBYTE0 (0x000000ff)
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#define I2C_TX_DATA_TBYTE1 (0x0000ff00)
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#define I2C_TX_DATA_TBYTE2 (0x00ff0000)
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#define I2C_TX_DATA_TBYTE3 (0xff000000)
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/* I2C_TX_DATA : Read/Write Bit Mask Definition */
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#define I2C_TX_DATA_RWMASK (0xffffffff)
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/* I2C_TX_DATA : Unused/Reserved bits Definition */
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#define I2C_TX_DATA_RESERVED (0x00000000)
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#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
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#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
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#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
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/* I2C status codes */
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#define TSI108_I2C_SUCCESS 0
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#define TSI108_I2C_PARAM_ERR 1
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#define TSI108_I2C_TIMEOUT_ERR 2
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#define TSI108_I2C_IF_BUSY 3
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#define TSI108_I2C_IF_ERROR 4
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#endif /* _TSI108_H_ */
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