mirror of
https://github.com/brain-hackers/u-boot-brain
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cdb6babec6
So far interrupt routing works pretty well for any on-chip devices on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, Linux kernel is smart enough to do interrupt swizzling and figure out device's irq using its parent bridge's interrupt routing info all the way up to its root port. In U-Boot all PCIe root ports' interrupts were routed to PIRQ E/F/G/H before, while actually all PCIe downstream ports received INTx are routed to PIRQ A/B/C/D directly and not configurable. Now we change this mapping so that any external PCIe device can work correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
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| .. | ||
| include | ||
| microcode | ||
| .gitignore | ||
| chromebook_link.dts | ||
| chromebox_panther.dts | ||
| crownbay.dts | ||
| galileo.dts | ||
| Makefile | ||
| minnowmax.dts | ||
| qemu-x86_i440fx.dts | ||
| qemu-x86_q35.dts | ||
| rtc.dtsi | ||
| serial.dtsi | ||
| skeleton.dtsi | ||