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https://github.com/brain-hackers/u-boot-brain
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![Wolfgang Denk](/assets/img/avatar_default.png)
should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005
1158 lines
25 KiB
ArmAsm
1158 lines
25 KiB
ArmAsm
/*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright (C) 2003 Motorola,Inc.
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* Xianghua Xiao<X.Xiao@motorola.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
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*
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* The processor starts at 0xfffffffc and the code is first executed in the
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* last 4K page(0xfffff000-0xffffffff) in flash/rom.
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*
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*/
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#include <config.h>
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#include <mpc85xx.h>
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#include <version.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#ifndef CONFIG_IDENT_STRING
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#define CONFIG_IDENT_STRING ""
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#endif
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#undef MSR_KERNEL
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#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
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/*
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* Set up GOT: Global Offset Table
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*
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* Use r14 to access the GOT
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*/
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START_GOT
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GOT_ENTRY(_GOT2_TABLE_)
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GOT_ENTRY(_FIXUP_TABLE_)
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GOT_ENTRY(_start)
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GOT_ENTRY(_start_of_vectors)
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GOT_ENTRY(_end_of_vectors)
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GOT_ENTRY(transfer_to_handler)
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GOT_ENTRY(__init_end)
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GOT_ENTRY(_end)
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GOT_ENTRY(__bss_start)
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END_GOT
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/*
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* e500 Startup -- after reset only the last 4KB of the effective
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* address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
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* section is located at THIS LAST page and basically does three
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* things: clear some registers, set up exception tables and
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* add more TLB entries for 'larger spaces'(e.g. the boot rom) to
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* continue the boot procedure.
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* Once the boot rom is mapped by TLB entries we can proceed
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* with normal startup.
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*
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*/
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.section .bootpg,"ax"
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.globl _start_e500
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_start_e500:
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mfspr r0, PVR
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lis r1, PVR_85xx_REV1@h
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ori r1, r1, PVR_85xx_REV1@l
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cmpw r0, r1
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bne 1f
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/* Semi-bogus errata fixup for Rev 1 */
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li r0,0x2000
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mtspr 977,r0
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/*
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* Before invalidating MMU L1/L2, read TLB1 Entry 0 and then
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* write it back immediately to fixup a Rev 1 bug (Errata CPU4)
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* for this initial TLB1 entry 0, otherwise the TLB1 entry 0
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* will be invalidated (incorrectly).
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*/
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lis r2,0x1000
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mtspr MAS0,r2
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tlbre
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tlbwe
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isync
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1:
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/*
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* Clear and set up some registers.
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* Note: Some registers need strict synchronization by
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* sync/mbar/msync/isync when being "mtspr".
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* BookE: isync before PID,tlbivax,tlbwe
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* BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe
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* E500: msync,isync before L1CSR0
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* E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,
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* L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],
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* SPEFCSR
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*/
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/* invalidate d-cache */
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mfspr r0,L1CSR0
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ori r0,r0,0x0002
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msync
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isync
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mtspr L1CSR0,r0
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isync
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/* disable d-cache */
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li r0,0x0
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mtspr L1CSR0,r0
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/* invalidate i-cache */
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mfspr r0,L1CSR1
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ori r0,r0,0x0002
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mtspr L1CSR1,r0
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isync
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/* disable i-cache */
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li r0,0x0
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mtspr L1CSR1,r0
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isync
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/* clear registers */
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li r0,0
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mtspr SRR0,r0
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mtspr SRR1,r0
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mtspr CSRR0,r0
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mtspr CSRR1,r0
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mtspr MCSRR0,r0
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mtspr MCSRR1,r0
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mtspr ESR,r0
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mtspr MCSR,r0
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mtspr DEAR,r0
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/* not needed and conflicts with some debuggers */
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/* mtspr DBCR0,r0 */
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mtspr DBCR1,r0
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mtspr DBCR2,r0
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/* not needed and conflicts with some debuggers */
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/* mtspr IAC1,r0 */
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/* mtspr IAC2,r0 */
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mtspr DAC1,r0
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mtspr DAC2,r0
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mfspr r1,DBSR
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mtspr DBSR,r1 /* Clear all valid bits */
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mtspr PID0,r0
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mtspr PID1,r0
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mtspr PID2,r0
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mtspr TCR,r0
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mtspr BUCSR,r0 /* disable branch prediction */
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mtspr MAS4,r0
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mtspr MAS6,r0
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#if defined(CONFIG_ENABLE_36BIT_PHYS)
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mtspr MAS7,r0
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#endif
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isync
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/* Setup interrupt vectors */
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lis r1,TEXT_BASE@h
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mtspr IVPR, r1
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li r1,0x0100
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mtspr IVOR0,r1 /* 0: Critical input */
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li r1,0x0200
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mtspr IVOR1,r1 /* 1: Machine check */
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li r1,0x0300
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mtspr IVOR2,r1 /* 2: Data storage */
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li r1,0x0400
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mtspr IVOR3,r1 /* 3: Instruction storage */
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li r1,0x0500
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mtspr IVOR4,r1 /* 4: External interrupt */
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li r1,0x0600
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mtspr IVOR5,r1 /* 5: Alignment */
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li r1,0x0700
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mtspr IVOR6,r1 /* 6: Program check */
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li r1,0x0800
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mtspr IVOR7,r1 /* 7: floating point unavailable */
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li r1,0x0900
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mtspr IVOR8,r1 /* 8: System call */
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/* 9: Auxiliary processor unavailable(unsupported) */
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li r1,0x0a00
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mtspr IVOR10,r1 /* 10: Decrementer */
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li r1,0x0b00
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mtspr IVOR11,r1 /* 11: Interval timer */
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li r1,0x0c00
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mtspr IVOR12,r1 /* 12: Watchdog timer */
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li r1,0x0d00
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mtspr IVOR13,r1 /* 13: Data TLB error */
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li r1,0x0e00
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mtspr IVOR14,r1 /* 14: Instruction TLB error */
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li r1,0x0f00
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mtspr IVOR15,r1 /* 15: Debug */
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/*
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* Invalidate MMU L1/L2
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*
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* Note: There is a fixup earlier for Errata CPU4 on
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* Rev 1 parts that must precede this MMU invalidation.
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*/
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li r2, 0x001e
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mtspr MMUCSR0, r2
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isync
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/*
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* Invalidate all TLB0 entries.
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*/
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li r3,4
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li r4,0
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tlbivax r4,r3
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/*
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* To avoid REV1 Errata CPU6 issues, make sure
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* the instruction following tlbivax is not a store.
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*/
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/*
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* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
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* 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
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* region before we can access any CCSR registers such as L2
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* registers, Local Access Registers,etc. We will also re-allocate
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* CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
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*
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* Please refer to board-specif directory for TLB1 entry configuration.
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* (e.g. board/<yourboard>/init.S)
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*
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*/
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bl tlb1_entry
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mr r5,r0
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li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */
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mtctr r1
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lwzu r4,0(r5) /* how many TLB1 entries we actually use */
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0: cmpwi r4,0
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beq 1f
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lwzu r0,4(r5)
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lwzu r1,4(r5)
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lwzu r2,4(r5)
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lwzu r3,4(r5)
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mtspr MAS0,r0
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mtspr MAS1,r1
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mtspr MAS2,r2
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mtspr MAS3,r3
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isync
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msync
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tlbwe
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isync
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addi r4,r4,-1
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bdnz 0b
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1:
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
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/* Special sequence needed to update CCSRBAR itself */
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lis r4, CFG_CCSRBAR_DEFAULT@h
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ori r4, r4, CFG_CCSRBAR_DEFAULT@l
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lis r5, CFG_CCSRBAR@h
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ori r5, r5, CFG_CCSRBAR@l
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srwi r6,r5,12
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stw r6, 0(r4)
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isync
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lis r5, 0xffff
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ori r5,r5,0xf000
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lwz r5, 0(r5)
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isync
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lis r3, CFG_CCSRBAR@h
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lwz r5, CFG_CCSRBAR@l(r3)
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isync
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#endif
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/* set up local access windows, defined at board/<boardname>/init.S */
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lis r7,CFG_CCSRBAR@h
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ori r7,r7,CFG_CCSRBAR@l
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bl law_entry
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mr r6,r0
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li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */
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mtctr r1
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lwzu r5,0(r6) /* how many windows we actually use */
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li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
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li r1,0x0c30
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0: cmpwi r5,0
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beq 1f
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lwzu r4,4(r6)
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lwzu r3,4(r6)
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stwx r4,r7,r2
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stwx r3,r7,r1
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addi r5,r5,-1
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addi r2,r2,0x0020
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addi r1,r1,0x0020
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bdnz 0b
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/* Jump out the last 4K page and continue to 'normal' start */
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1: bl 3f
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b _start
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3: li r0,0
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mtspr SRR1,r0 /* Keep things disabled for now */
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mflr r1
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mtspr SRR0,r1
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rfi
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/*
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* r3 - 1st arg to board_init(): IMMP pointer
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* r4 - 2nd arg to board_init(): boot flag
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*/
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.text
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.long 0x27051956 /* U-BOOT Magic Number */
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.globl version_string
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version_string:
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.ascii U_BOOT_VERSION
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.ascii " (", __DATE__, " - ", __TIME__, ")"
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.ascii CONFIG_IDENT_STRING, "\0"
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. = EXC_OFF_SYS_RESET
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.globl _start
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_start:
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/* Clear and set up some registers. */
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li r0,0x0000
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lis r1,0xffff
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mtspr DEC,r0 /* prevent dec exceptions */
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mttbl r0 /* prevent fit & wdt exceptions */
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mttbu r0
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mtspr TSR,r1 /* clear all timer exception status */
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mtspr TCR,r0 /* disable all */
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mtspr ESR,r0 /* clear exception syndrome register */
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mtspr MCSR,r0 /* machine check syndrome register */
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mtxer r0 /* clear integer exception register */
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lis r1,0x0002 /* set CE bit (Critical Exceptions) */
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ori r1,r1,0x1200 /* set ME/DE bit */
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mtmsr r1 /* change MSR */
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isync
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/* Enable Time Base and Select Time Base Clock */
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lis r0,HID0_EMCP@h /* Enable machine check */
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ori r0,r0,0x4000 /* time base is processor clock */
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#if defined(CONFIG_ENABLE_36BIT_PHYS)
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ori r0,r0,0x0080 /* enable MAS7 updates */
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#endif
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mtspr HID0,r0
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#if defined(CONFIG_ADDR_STREAMING)
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li r0,0x3000
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#else
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li r0,0x1000
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#endif
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mtspr HID1,r0
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/* Enable Branch Prediction */
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#if defined(CONFIG_BTB)
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li r0,0x201 /* BBFI = 1, BPEN = 1 */
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mtspr BUCSR,r0
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#endif
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#if defined(CFG_INIT_DBCR)
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lis r1,0xffff
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ori r1,r1,0xffff
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mtspr DBSR,r1 /* Clear all status bits */
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lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */
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ori r0,r0,CFG_INIT_DBCR@l
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mtspr DBCR0,r0
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#endif
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/* L1 DCache is used for initial RAM */
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mfspr r2, L1CSR0
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ori r2, r2, 0x0003
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oris r2, r2, 0x0001
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mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */
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isync
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/* Allocate Initial RAM in data cache.
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*/
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lis r3, CFG_INIT_RAM_ADDR@h
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ori r3, r3, CFG_INIT_RAM_ADDR@l
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li r2, 512 /* 512*32=16K */
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mtctr r2
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li r0, 0
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1:
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dcbz r0, r3
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dcbtls 0,r0, r3
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addi r3, r3, 32
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bdnz 1b
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#ifndef CFG_RAMBOOT
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/* Calculate absolute address in FLASH and jump there */
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/*--------------------------------------------------------------*/
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lis r3, CFG_MONITOR_BASE@h
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ori r3, r3, CFG_MONITOR_BASE@l
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addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
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mtlr r3
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blr
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in_flash:
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#endif /* CFG_RAMBOOT */
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/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
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lis r1,CFG_INIT_RAM_ADDR@h
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ori r1,r1,CFG_INIT_SP_OFFSET@l
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li r0,0
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stwu r0,-4(r1)
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stwu r0,-4(r1) /* Terminate call chain */
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stwu r1,-8(r1) /* Save back chain and move SP */
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lis r0,RESET_VECTOR@h /* Address of reset vector */
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ori r0,r0, RESET_VECTOR@l
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stwu r1,-8(r1) /* Save back chain and move SP */
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stw r0,+12(r1) /* Save return addr (underflow vect) */
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GET_GOT
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bl cpu_init_f
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bl icache_enable
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bl board_init_f
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isync
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/* --FIXME-- machine check with MCSRRn and rfmci */
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.globl _start_of_vectors
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_start_of_vectors:
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#if 0
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/* Critical input. */
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CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException)
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#endif
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/* Machine check --FIXME-- Should be MACH_EXCEPTION */
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CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
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/* Data Storage exception. */
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STD_EXCEPTION(0x0300, DataStorage, UnknownException)
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/* Instruction Storage exception. */
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STD_EXCEPTION(0x0400, InstStorage, UnknownException)
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/* External Interrupt exception. */
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STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException)
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/* Alignment exception. */
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. = 0x0600
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Alignment:
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EXCEPTION_PROLOG
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mfspr r4,DAR
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stw r4,_DAR(r21)
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mfspr r5,DSISR
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stw r5,_DSISR(r21)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_Alignment:
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.long AlignmentException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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/* Program check exception */
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. = 0x0700
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ProgramCheck:
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EXCEPTION_PROLOG
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_ProgramCheck:
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.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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/* No FPU on MPC85xx. This exception is not supposed to happen.
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*/
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STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
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. = 0x0900
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/*
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* r0 - SYSCALL number
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* r3-... arguments
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*/
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SystemCall:
|
|
addis r11,r0,0 /* get functions table addr */
|
|
ori r11,r11,0 /* Note: this code is patched in trap_init */
|
|
addis r12,r0,0 /* get number of functions */
|
|
ori r12,r12,0
|
|
|
|
cmplw 0, r0, r12
|
|
bge 1f
|
|
|
|
rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
|
|
add r11,r11,r0
|
|
lwz r11,0(r11)
|
|
|
|
li r20,0xd00-4 /* Get stack pointer */
|
|
lwz r12,0(r20)
|
|
subi r12,r12,12 /* Adjust stack pointer */
|
|
li r0,0xc00+_end_back-SystemCall
|
|
cmplw 0, r0, r12 /* Check stack overflow */
|
|
bgt 1f
|
|
stw r12,0(r20)
|
|
|
|
mflr r0
|
|
stw r0,0(r12)
|
|
mfspr r0,SRR0
|
|
stw r0,4(r12)
|
|
mfspr r0,SRR1
|
|
stw r0,8(r12)
|
|
|
|
li r12,0xc00+_back-SystemCall
|
|
mtlr r12
|
|
mtspr SRR0,r11
|
|
|
|
1: SYNC
|
|
rfi
|
|
_back:
|
|
|
|
mfmsr r11 /* Disable interrupts */
|
|
li r12,0
|
|
ori r12,r12,MSR_EE
|
|
andc r11,r11,r12
|
|
SYNC /* Some chip revs need this... */
|
|
mtmsr r11
|
|
SYNC
|
|
|
|
li r12,0xd00-4 /* restore regs */
|
|
lwz r12,0(r12)
|
|
|
|
lwz r11,0(r12)
|
|
mtlr r11
|
|
lwz r11,4(r12)
|
|
mtspr SRR0,r11
|
|
lwz r11,8(r12)
|
|
mtspr SRR1,r11
|
|
|
|
addi r12,r12,12 /* Adjust stack pointer */
|
|
li r20,0xd00-4
|
|
stw r12,0(r20)
|
|
|
|
SYNC
|
|
rfi
|
|
_end_back:
|
|
|
|
STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
|
|
STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
|
|
STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
|
|
|
|
STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
|
|
STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
|
|
|
|
CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
|
|
|
|
.globl _end_of_vectors
|
|
_end_of_vectors:
|
|
|
|
|
|
. = 0x2100
|
|
|
|
/*
|
|
* This code finishes saving the registers to the exception frame
|
|
* and jumps to the appropriate handler for the exception.
|
|
* Register r21 is pointer into trap frame, r1 has new stack pointer.
|
|
*/
|
|
.globl transfer_to_handler
|
|
transfer_to_handler:
|
|
stw r22,_NIP(r21)
|
|
lis r22,MSR_POW@h
|
|
andc r23,r23,r22
|
|
stw r23,_MSR(r21)
|
|
SAVE_GPR(7, r21)
|
|
SAVE_4GPRS(8, r21)
|
|
SAVE_8GPRS(12, r21)
|
|
SAVE_8GPRS(24, r21)
|
|
|
|
mflr r23
|
|
andi. r24,r23,0x3f00 /* get vector offset */
|
|
stw r24,TRAP(r21)
|
|
li r22,0
|
|
stw r22,RESULT(r21)
|
|
mtspr SPRG2,r22 /* r1 is now kernel sp */
|
|
|
|
lwz r24,0(r23) /* virtual address of handler */
|
|
lwz r23,4(r23) /* where to go when done */
|
|
mtspr SRR0,r24
|
|
mtspr SRR1,r20
|
|
mtlr r23
|
|
SYNC
|
|
rfi /* jump to handler, enable MMU */
|
|
|
|
int_return:
|
|
mfmsr r28 /* Disable interrupts */
|
|
li r4,0
|
|
ori r4,r4,MSR_EE
|
|
andc r28,r28,r4
|
|
SYNC /* Some chip revs need this... */
|
|
mtmsr r28
|
|
SYNC
|
|
lwz r2,_CTR(r1)
|
|
lwz r0,_LINK(r1)
|
|
mtctr r2
|
|
mtlr r0
|
|
lwz r2,_XER(r1)
|
|
lwz r0,_CCR(r1)
|
|
mtspr XER,r2
|
|
mtcrf 0xFF,r0
|
|
REST_10GPRS(3, r1)
|
|
REST_10GPRS(13, r1)
|
|
REST_8GPRS(23, r1)
|
|
REST_GPR(31, r1)
|
|
lwz r2,_NIP(r1) /* Restore environment */
|
|
lwz r0,_MSR(r1)
|
|
mtspr SRR0,r2
|
|
mtspr SRR1,r0
|
|
lwz r0,GPR0(r1)
|
|
lwz r2,GPR2(r1)
|
|
lwz r1,GPR1(r1)
|
|
SYNC
|
|
rfi
|
|
|
|
crit_return:
|
|
mfmsr r28 /* Disable interrupts */
|
|
li r4,0
|
|
ori r4,r4,MSR_EE
|
|
andc r28,r28,r4
|
|
SYNC /* Some chip revs need this... */
|
|
mtmsr r28
|
|
SYNC
|
|
lwz r2,_CTR(r1)
|
|
lwz r0,_LINK(r1)
|
|
mtctr r2
|
|
mtlr r0
|
|
lwz r2,_XER(r1)
|
|
lwz r0,_CCR(r1)
|
|
mtspr XER,r2
|
|
mtcrf 0xFF,r0
|
|
REST_10GPRS(3, r1)
|
|
REST_10GPRS(13, r1)
|
|
REST_8GPRS(23, r1)
|
|
REST_GPR(31, r1)
|
|
lwz r2,_NIP(r1) /* Restore environment */
|
|
lwz r0,_MSR(r1)
|
|
mtspr 990,r2 /* SRR2 */
|
|
mtspr 991,r0 /* SRR3 */
|
|
lwz r0,GPR0(r1)
|
|
lwz r2,GPR2(r1)
|
|
lwz r1,GPR1(r1)
|
|
SYNC
|
|
rfci
|
|
|
|
/* Cache functions.
|
|
*/
|
|
invalidate_icache:
|
|
mfspr r0,L1CSR1
|
|
ori r0,r0,0x0002
|
|
mtspr L1CSR1,r0
|
|
isync
|
|
blr /* entire I cache */
|
|
|
|
invalidate_dcache:
|
|
mfspr r0,L1CSR0
|
|
ori r0,r0,0x0002
|
|
msync
|
|
isync
|
|
mtspr L1CSR0,r0
|
|
isync
|
|
blr
|
|
|
|
.globl icache_enable
|
|
icache_enable:
|
|
mflr r8
|
|
bl invalidate_icache
|
|
mtlr r8
|
|
isync
|
|
mfspr r4,L1CSR1
|
|
ori r4,r4,0x0001
|
|
oris r4,r4,0x0001
|
|
mtspr L1CSR1,r4
|
|
isync
|
|
blr
|
|
|
|
.globl icache_disable
|
|
icache_disable:
|
|
mfspr r0,L1CSR1
|
|
lis r1,0xfffffffe@h
|
|
ori r1,r1,0xfffffffe@l
|
|
and r0,r0,r1
|
|
mtspr L1CSR1,r0
|
|
isync
|
|
blr
|
|
|
|
.globl icache_status
|
|
icache_status:
|
|
mfspr r3,L1CSR1
|
|
andi. r3,r3,1
|
|
blr
|
|
|
|
.globl dcache_enable
|
|
dcache_enable:
|
|
mflr r8
|
|
bl invalidate_dcache
|
|
mtlr r8
|
|
isync
|
|
mfspr r0,L1CSR0
|
|
ori r0,r0,0x0001
|
|
oris r0,r0,0x0001
|
|
msync
|
|
isync
|
|
mtspr L1CSR0,r0
|
|
isync
|
|
blr
|
|
|
|
.globl dcache_disable
|
|
dcache_disable:
|
|
mfspr r0,L1CSR0
|
|
lis r1,0xfffffffe@h
|
|
ori r1,r1,0xfffffffe@l
|
|
and r0,r0,r1
|
|
msync
|
|
isync
|
|
mtspr L1CSR0,r0
|
|
isync
|
|
blr
|
|
|
|
.globl dcache_status
|
|
dcache_status:
|
|
mfspr r3,L1CSR0
|
|
andi. r3,r3,1
|
|
blr
|
|
|
|
.globl get_pir
|
|
get_pir:
|
|
mfspr r3, PIR
|
|
blr
|
|
|
|
.globl get_pvr
|
|
get_pvr:
|
|
mfspr r3, PVR
|
|
blr
|
|
|
|
.globl get_svr
|
|
get_svr:
|
|
mfspr r3, SVR
|
|
blr
|
|
|
|
.globl wr_tcr
|
|
wr_tcr:
|
|
mtspr TCR, r3
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: in8 */
|
|
/* Description: Input 8 bits */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl in8
|
|
in8:
|
|
lbz r3,0x0000(r3)
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: out8 */
|
|
/* Description: Output 8 bits */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl out8
|
|
out8:
|
|
stb r4,0x0000(r3)
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: out16 */
|
|
/* Description: Output 16 bits */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl out16
|
|
out16:
|
|
sth r4,0x0000(r3)
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: out16r */
|
|
/* Description: Byte reverse and output 16 bits */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl out16r
|
|
out16r:
|
|
sthbrx r4,r0,r3
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: out32 */
|
|
/* Description: Output 32 bits */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl out32
|
|
out32:
|
|
stw r4,0x0000(r3)
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: out32r */
|
|
/* Description: Byte reverse and output 32 bits */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl out32r
|
|
out32r:
|
|
stwbrx r4,r0,r3
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: in16 */
|
|
/* Description: Input 16 bits */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl in16
|
|
in16:
|
|
lhz r3,0x0000(r3)
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: in16r */
|
|
/* Description: Input 16 bits and byte reverse */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl in16r
|
|
in16r:
|
|
lhbrx r3,r0,r3
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: in32 */
|
|
/* Description: Input 32 bits */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl in32
|
|
in32:
|
|
lwz 3,0x0000(3)
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: in32r */
|
|
/* Description: Input 32 bits and byte reverse */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl in32r
|
|
in32r:
|
|
lwbrx r3,r0,r3
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: ppcDcbf */
|
|
/* Description: Data Cache block flush */
|
|
/* Input: r3 = effective address */
|
|
/* Output: none. */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl ppcDcbf
|
|
ppcDcbf:
|
|
dcbf r0,r3
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: ppcDcbi */
|
|
/* Description: Data Cache block Invalidate */
|
|
/* Input: r3 = effective address */
|
|
/* Output: none. */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl ppcDcbi
|
|
ppcDcbi:
|
|
dcbi r0,r3
|
|
blr
|
|
|
|
/*--------------------------------------------------------------------------
|
|
* Function: ppcDcbz
|
|
* Description: Data Cache block zero.
|
|
* Input: r3 = effective address
|
|
* Output: none.
|
|
*-------------------------------------------------------------------------- */
|
|
|
|
.globl ppcDcbz
|
|
ppcDcbz:
|
|
dcbz r0,r3
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
/* Function: ppcSync */
|
|
/* Description: Processor Synchronize */
|
|
/* Input: none. */
|
|
/* Output: none. */
|
|
/*------------------------------------------------------------------------------- */
|
|
.globl ppcSync
|
|
ppcSync:
|
|
sync
|
|
blr
|
|
|
|
/*------------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* void relocate_code (addr_sp, gd, addr_moni)
|
|
*
|
|
* This "function" does not return, instead it continues in RAM
|
|
* after relocating the monitor code.
|
|
*
|
|
* r3 = dest
|
|
* r4 = src
|
|
* r5 = length in bytes
|
|
* r6 = cachelinesize
|
|
*/
|
|
.globl relocate_code
|
|
relocate_code:
|
|
mr r1, r3 /* Set new stack pointer */
|
|
mr r9, r4 /* Save copy of Init Data pointer */
|
|
mr r10, r5 /* Save copy of Destination Address */
|
|
|
|
mr r3, r5 /* Destination Address */
|
|
lis r4, CFG_MONITOR_BASE@h /* Source Address */
|
|
ori r4, r4, CFG_MONITOR_BASE@l
|
|
lwz r5,GOT(__init_end)
|
|
sub r5,r5,r4
|
|
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
|
|
|
|
/*
|
|
* Fix GOT pointer:
|
|
*
|
|
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
|
|
*
|
|
* Offset:
|
|
*/
|
|
sub r15, r10, r4
|
|
|
|
/* First our own GOT */
|
|
add r14, r14, r15
|
|
/* the the one used by the C code */
|
|
add r30, r30, r15
|
|
|
|
/*
|
|
* Now relocate code
|
|
*/
|
|
|
|
cmplw cr1,r3,r4
|
|
addi r0,r5,3
|
|
srwi. r0,r0,2
|
|
beq cr1,4f /* In place copy is not necessary */
|
|
beq 7f /* Protect against 0 count */
|
|
mtctr r0
|
|
bge cr1,2f
|
|
|
|
la r8,-4(r4)
|
|
la r7,-4(r3)
|
|
1: lwzu r0,4(r8)
|
|
stwu r0,4(r7)
|
|
bdnz 1b
|
|
b 4f
|
|
|
|
2: slwi r0,r0,2
|
|
add r8,r4,r0
|
|
add r7,r3,r0
|
|
3: lwzu r0,-4(r8)
|
|
stwu r0,-4(r7)
|
|
bdnz 3b
|
|
|
|
/*
|
|
* Now flush the cache: note that we must start from a cache aligned
|
|
* address. Otherwise we might miss one cache line.
|
|
*/
|
|
4: cmpwi r6,0
|
|
add r5,r3,r5
|
|
beq 7f /* Always flush prefetch queue in any case */
|
|
subi r0,r6,1
|
|
andc r3,r3,r0
|
|
mr r4,r3
|
|
5: dcbst 0,r4
|
|
add r4,r4,r6
|
|
cmplw r4,r5
|
|
blt 5b
|
|
sync /* Wait for all dcbst to complete on bus */
|
|
mr r4,r3
|
|
6: icbi 0,r4
|
|
add r4,r4,r6
|
|
cmplw r4,r5
|
|
blt 6b
|
|
7: sync /* Wait for all icbi to complete on bus */
|
|
isync
|
|
|
|
/*
|
|
* Re-point the IVPR at RAM
|
|
*/
|
|
mtspr IVPR,r10
|
|
|
|
/*
|
|
* We are done. Do not return, instead branch to second part of board
|
|
* initialization, now running from RAM.
|
|
*/
|
|
|
|
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
|
|
mtlr r0
|
|
blr /* NEVER RETURNS! */
|
|
|
|
in_ram:
|
|
|
|
/*
|
|
* Relocation Function, r14 point to got2+0x8000
|
|
*
|
|
* Adjust got2 pointers, no need to check for 0, this code
|
|
* already puts a few entries in the table.
|
|
*/
|
|
li r0,__got2_entries@sectoff@l
|
|
la r3,GOT(_GOT2_TABLE_)
|
|
lwz r11,GOT(_GOT2_TABLE_)
|
|
mtctr r0
|
|
sub r11,r3,r11
|
|
addi r3,r3,-4
|
|
1: lwzu r0,4(r3)
|
|
add r0,r0,r11
|
|
stw r0,0(r3)
|
|
bdnz 1b
|
|
|
|
/*
|
|
* Now adjust the fixups and the pointers to the fixups
|
|
* in case we need to move ourselves again.
|
|
*/
|
|
2: li r0,__fixup_entries@sectoff@l
|
|
lwz r3,GOT(_FIXUP_TABLE_)
|
|
cmpwi r0,0
|
|
mtctr r0
|
|
addi r3,r3,-4
|
|
beq 4f
|
|
3: lwzu r4,4(r3)
|
|
lwzux r0,r4,r11
|
|
add r0,r0,r11
|
|
stw r10,0(r3)
|
|
stw r0,0(r4)
|
|
bdnz 3b
|
|
4:
|
|
clear_bss:
|
|
/*
|
|
* Now clear BSS segment
|
|
*/
|
|
lwz r3,GOT(__bss_start)
|
|
lwz r4,GOT(_end)
|
|
|
|
cmplw 0, r3, r4
|
|
beq 6f
|
|
|
|
li r0, 0
|
|
5:
|
|
stw r0, 0(r3)
|
|
addi r3, r3, 4
|
|
cmplw 0, r3, r4
|
|
bne 5b
|
|
6:
|
|
|
|
mr r3, r9 /* Init Data pointer */
|
|
mr r4, r10 /* Destination Address */
|
|
bl board_init_r
|
|
|
|
/*
|
|
* Copy exception vector code to low memory
|
|
*
|
|
* r3: dest_addr
|
|
* r7: source address, r8: end address, r9: target address
|
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*/
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.globl trap_init
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trap_init:
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lwz r7, GOT(_start)
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lwz r8, GOT(_end_of_vectors)
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|
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li r9, 0x100 /* reset vector always at 0x100 */
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|
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cmplw 0, r7, r8
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bgelr /* return if r7>=r8 - just in case */
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mflr r4 /* save link register */
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1:
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lwz r0, 0(r7)
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stw r0, 0(r9)
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addi r7, r7, 4
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addi r9, r9, 4
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cmplw 0, r7, r8
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bne 1b
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|
|
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/*
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* relocate `hdlr' and `int_return' entries
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*/
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li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
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bl trap_reloc
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li r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET
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bl trap_reloc
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li r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET
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bl trap_reloc
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li r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET
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|
bl trap_reloc
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li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
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|
bl trap_reloc
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li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
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|
bl trap_reloc
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li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
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|
bl trap_reloc
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li r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET
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bl trap_reloc
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li r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET
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li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
|
|
2:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
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|
cmplw 0, r7, r8
|
|
blt 2b
|
|
|
|
lis r7,0x0
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|
mtspr IVPR, r7
|
|
|
|
mtlr r4 /* restore link register */
|
|
blr
|
|
|
|
/*
|
|
* Function: relocate entries for one exception vector
|
|
*/
|
|
trap_reloc:
|
|
lwz r0, 0(r7) /* hdlr ... */
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|
add r0, r0, r3 /* ... += dest_addr */
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|
stw r0, 0(r7)
|
|
|
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lwz r0, 4(r7) /* int_return ... */
|
|
add r0, r0, r3 /* ... += dest_addr */
|
|
stw r0, 4(r7)
|
|
|
|
blr
|
|
|
|
#ifdef CFG_INIT_RAM_LOCK
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|
.globl unlock_ram_in_cache
|
|
unlock_ram_in_cache:
|
|
/* invalidate the INIT_RAM section */
|
|
lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
|
|
ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
|
|
li r2,512
|
|
mtctr r2
|
|
1: icbi r0, r3
|
|
dcbi r0, r3
|
|
addi r3, r3, 32
|
|
bdnz 1b
|
|
sync /* Wait for all icbi to complete on bus */
|
|
isync
|
|
blr
|
|
#endif
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