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The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>
24 lines
579 B
Plaintext
24 lines
579 B
Plaintext
Intel LPC Device Binding
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========================
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The device tree node which describes the operation of the Intel Low Pin
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Count device is as follows:
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Required properties :
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- compatible = "intel,lpc"
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- gen-dec : Specifies the values for the gen-dec registers. Up to four cell
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pairs can be provided - the first of each pair is the base address and
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the second is the size. These are written into the GENx_DEC registers of
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the LPC device
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Example
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-------
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lpc {
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compatible = "intel,lpc";
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#address-cells = <1>;
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#size-cells = <1>;
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gen-dec = <0x800 0xfc 0x900 0xfc>;
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};
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