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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
At present we go through various contortions to store the I2C's chip address in its private data. This only exists when the chip is active so must be set up when it is probed. Until the device is probed we don't actually record what address it will appear on. However, now that we can support per-child platform data, we can use that instead. This allows us to set up the address when the child is bound, and avoid the messy contortions. Unfortunately this is a fairly large change and it seems to be difficult to break it down further. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
368 lines
8.5 KiB
C
368 lines
8.5 KiB
C
/*
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* Copyright (C) 2014 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <dm/device.h>
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#include <dm/root.h>
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#include <i2c.h>
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#include <fdtdec.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct uniphier_fi2c_regs {
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u32 cr; /* control register */
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#define I2C_CR_MST (1 << 3) /* master mode */
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#define I2C_CR_STA (1 << 2) /* start condition */
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#define I2C_CR_STO (1 << 1) /* stop condition */
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#define I2C_CR_NACK (1 << 0) /* not ACK */
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u32 dttx; /* send FIFO (write-only) */
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#define dtrx dttx /* receive FIFO (read-only) */
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#define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */
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#define I2C_DTTX_RD (1 << 0) /* read */
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u32 __reserved; /* no register at offset 0x08 */
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u32 slad; /* slave address */
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u32 cyc; /* clock cycle control */
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u32 lctl; /* clock low period control */
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u32 ssut; /* restart/stop setup time control */
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u32 dsut; /* data setup time control */
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u32 intr; /* interrupt status */
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u32 ie; /* interrupt enable */
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u32 ic; /* interrupt clear */
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#define I2C_INT_TE (1 << 9) /* TX FIFO empty */
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#define I2C_INT_RB (1 << 4) /* received specified bytes */
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#define I2C_INT_NA (1 << 2) /* no answer */
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#define I2C_INT_AL (1 << 1) /* arbitration lost */
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u32 sr; /* status register */
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#define I2C_SR_DB (1 << 12) /* device busy */
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#define I2C_SR_BB (1 << 8) /* bus busy */
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#define I2C_SR_RFF (1 << 3) /* Rx FIFO full */
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#define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */
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#define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */
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#define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */
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u32 __reserved2; /* no register at offset 0x30 */
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u32 rst; /* reset control */
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#define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */
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#define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */
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#define I2C_RST_RST (1 << 0) /* forcible bus reset */
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u32 bm; /* bus monitor */
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u32 noise; /* noise filter control */
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u32 tbc; /* Tx byte count setting */
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u32 rbc; /* Rx byte count setting */
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u32 tbcm; /* Tx byte count monitor */
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u32 rbcm; /* Rx byte count monitor */
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u32 brst; /* bus reset */
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#define I2C_BRST_FOEN (1 << 1) /* normal operation */
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#define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */
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};
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#define FIOCLK 50000000
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struct uniphier_fi2c_dev {
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struct uniphier_fi2c_regs __iomem *regs; /* register base */
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unsigned long fioclk; /* internal operation clock */
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unsigned long timeout; /* time out (us) */
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};
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static int poll_status(u32 __iomem *reg, u32 flag)
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{
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int wait = 1000000; /* 1 sec is long enough */
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while (readl(reg) & flag) {
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if (wait-- < 0)
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return -EREMOTEIO;
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udelay(1);
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}
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return 0;
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}
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static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)
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{
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int ret;
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/* bus forcible reset */
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writel(I2C_RST_RST, ®s->rst);
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ret = poll_status(®s->rst, I2C_RST_RST);
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if (ret < 0)
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debug("error: fail to reset I2C controller\n");
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return ret;
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}
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static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs)
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{
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int ret;
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ret = poll_status(®s->sr, I2C_SR_DB);
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if (ret < 0) {
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debug("error: device busy too long. reset...\n");
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ret = reset_bus(regs);
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}
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return ret;
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}
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static int uniphier_fi2c_probe(struct udevice *dev)
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{
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fdt_addr_t addr;
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fdt_size_t size;
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struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
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int ret;
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addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
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&size);
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priv->regs = map_sysmem(addr, size);
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if (!priv->regs)
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return -ENOMEM;
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priv->fioclk = FIOCLK;
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/* bus forcible reset */
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ret = reset_bus(priv->regs);
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if (ret < 0)
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return ret;
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writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
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return 0;
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}
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static int uniphier_fi2c_remove(struct udevice *dev)
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{
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struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
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unmap_sysmem(priv->regs);
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return 0;
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}
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static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags,
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bool *stop)
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{
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u32 irq;
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unsigned long wait = dev->timeout;
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int ret = -EREMOTEIO;
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do {
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udelay(1);
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irq = readl(&dev->regs->intr);
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} while (!(irq & flags) && wait--);
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if (wait < 0) {
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debug("error: time out\n");
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return ret;
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}
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if (irq & I2C_INT_AL) {
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debug("error: arbitration lost\n");
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*stop = false;
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return ret;
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}
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if (irq & I2C_INT_NA) {
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debug("error: no answer\n");
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return ret;
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}
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return 0;
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}
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static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret)
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{
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int ret;
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debug("stop condition\n");
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writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr);
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ret = poll_status(&dev->regs->sr, I2C_SR_DB);
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if (ret < 0)
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debug("error: device busy after operation\n");
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return old_ret ? old_ret : ret;
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}
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static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr,
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uint len, const u8 *buf, bool *stop)
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{
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int ret;
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const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL;
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struct uniphier_fi2c_regs __iomem *regs = dev->regs;
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debug("%s: addr = %x, len = %d\n", __func__, addr, len);
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writel(I2C_DTTX_CMD | addr << 1, ®s->dttx);
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writel(irq_flags, ®s->ie);
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writel(irq_flags, ®s->ic);
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debug("start condition\n");
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writel(I2C_CR_MST | I2C_CR_STA, ®s->cr);
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ret = wait_for_irq(dev, irq_flags, stop);
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if (ret < 0)
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goto error;
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while (len--) {
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debug("sending %x\n", *buf);
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writel(*buf++, ®s->dttx);
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writel(irq_flags, ®s->ic);
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ret = wait_for_irq(dev, irq_flags, stop);
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if (ret < 0)
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goto error;
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}
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error:
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writel(irq_flags, ®s->ic);
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if (*stop)
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ret = issue_stop(dev, ret);
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return ret;
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}
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static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr,
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uint len, u8 *buf, bool *stop)
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{
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int ret = 0;
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const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL;
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struct uniphier_fi2c_regs __iomem *regs = dev->regs;
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debug("%s: addr = %x, len = %d\n", __func__, addr, len);
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/*
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* In case 'len == 0', only the slave address should be sent
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* for probing, which is covered by the transmit function.
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*/
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if (len == 0)
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return uniphier_fi2c_transmit(dev, addr, len, buf, stop);
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writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, ®s->dttx);
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writel(0, ®s->rbc);
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writel(irq_flags, ®s->ie);
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writel(irq_flags, ®s->ic);
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debug("start condition\n");
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writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0),
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®s->cr);
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while (len--) {
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ret = wait_for_irq(dev, irq_flags, stop);
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if (ret < 0)
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goto error;
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*buf++ = readl(®s->dtrx);
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debug("received %x\n", *(buf - 1));
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if (len == 1)
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writel(I2C_CR_MST | I2C_CR_NACK, ®s->cr);
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writel(irq_flags, ®s->ic);
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}
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error:
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writel(irq_flags, ®s->ic);
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if (*stop)
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ret = issue_stop(dev, ret);
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return ret;
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}
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static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg,
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int nmsgs)
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{
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int ret;
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struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
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bool stop;
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ret = check_device_busy(dev->regs);
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if (ret < 0)
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return ret;
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for (; nmsgs > 0; nmsgs--, msg++) {
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/* If next message is read, skip the stop condition */
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stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
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if (msg->flags & I2C_M_RD)
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ret = uniphier_fi2c_receive(dev, msg->addr, msg->len,
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msg->buf, &stop);
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else
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ret = uniphier_fi2c_transmit(dev, msg->addr, msg->len,
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msg->buf, &stop);
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if (ret < 0)
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break;
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}
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return ret;
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}
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static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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{
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int ret;
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unsigned int clk_count;
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struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
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struct uniphier_fi2c_regs __iomem *regs = dev->regs;
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/* max supported frequency is 400 kHz */
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if (speed > 400000)
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return -EINVAL;
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ret = check_device_busy(dev->regs);
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if (ret < 0)
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return ret;
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/* make sure the bus is idle when changing the frequency */
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writel(I2C_BRST_RSCLO, ®s->brst);
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clk_count = dev->fioclk / speed;
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writel(clk_count, ®s->cyc);
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writel(clk_count / 2, ®s->lctl);
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writel(clk_count / 2, ®s->ssut);
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writel(clk_count / 16, ®s->dsut);
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writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, ®s->brst);
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/*
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* Theoretically, each byte can be transferred in
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* 1000000 * 9 / speed usec.
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* This time out value is long enough.
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*/
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dev->timeout = 100000000L / speed;
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return 0;
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}
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static const struct dm_i2c_ops uniphier_fi2c_ops = {
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.xfer = uniphier_fi2c_xfer,
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.set_bus_speed = uniphier_fi2c_set_bus_speed,
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};
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static const struct udevice_id uniphier_fi2c_of_match[] = {
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{ .compatible = "panasonic,uniphier-fi2c" },
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{},
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};
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U_BOOT_DRIVER(uniphier_fi2c) = {
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.name = "uniphier-fi2c",
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.id = UCLASS_I2C,
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.of_match = uniphier_fi2c_of_match,
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.probe = uniphier_fi2c_probe,
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.remove = uniphier_fi2c_remove,
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.priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev),
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.ops = &uniphier_fi2c_ops,
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};
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