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u-boot-brain/board/sharp/pwg5300/iomux.c

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// SPDX-License-Identifier: GPL-2.0+
/*
* SHARP PW-G5300 IOMUX setup
*
* Copyright (C) 2021 Suguru Saito <sg.sgch07@gmail.com>
* Copyright (C) 2020 Takumi Sueda <puhitaku@gmail.com>
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx28.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SSP1 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_LCD (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_GPIO (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SAIF (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
const iomux_cfg_t iomux_setup[] = {
/* MMC0 */
MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_CMD__SSP0_CMD |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_SCK__SSP0_SCK |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
/* write protect */
//MX28_PAD_SSP1_SCK__GPIO_2_12,
/* eMMC power enable */
MX28_PAD_PWM3__GPIO_3_28 |
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
/* MMC1 */
MX28_PAD_GPMI_D00__SSP1_D0 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_D01__SSP1_D1 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_D02__SSP1_D2 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_D03__SSP1_D3 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_RDY1__SSP1_CMD | MUX_CONFIG_SSP1,
/*MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),*/
MX28_PAD_GPMI_WRN__SSP1_SCK | MUX_CONFIG_SSP1,
/* SD slot power enable */
MX28_PAD_SSP2_SS2__GPIO_2_21 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
/* USB */
/*MX28_PAD_GPMI_RDY0__USB0_ID |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULLUP),*/
/* ENET0 */
MX28_PAD_ENET0_COL__GPIO_4_14 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_CRS__GPIO_4_15 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TXD3__GPIO_4_12 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TXD2__GPIO_4_11 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RXD2__GPIO_4_9 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TXD1__GPIO_4_8 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TXD0__GPIO_4_7 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TX_EN__GPIO_4_6 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RXD1__GPIO_4_4 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RXD0__GPIO_4_3 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RX_EN__GPIO_4_2 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_MDIO__GPIO_4_1 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_MDC__GPIO_4_0 | MUX_CONFIG_GPIO,
/* EMI */
MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
/* SSP2 */
MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_SS0__SSP2_D3 | MUX_CONFIG_SSP2,
/* SLCD reset? */
MX28_PAD_SSP2_MISO__GPIO_2_18 | MUX_CONFIG_GPIO,
/* SLCD backlight control */
MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_GPIO,
/* I2C */
MX28_PAD_I2C0_SCL__I2C0_SCL,
MX28_PAD_I2C0_SDA__I2C0_SDA,
/* DUART */
MX28_PAD_PWM1__DUART_TX,
MX28_PAD_PWM0__DUART_RX,
/* LCD */
MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
MX28_PAD_LCD_RD_E__LCD_RD_E | MUX_CONFIG_LCD,
MX28_PAD_LCD_WR_RWN__LCD_WR_RWN | MUX_CONFIG_LCD,
MX28_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
/* LCD Regulator EN? */
MX28_PAD_GPMI_ALE__GPIO_0_26 |
(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP),
MX28_PAD_GPMI_CLE__GPIO_0_27 |
(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP),
/* LCD ? */
MX28_PAD_ENET_CLK__GPIO_4_16 | MUX_CONFIG_LCD,
/* LCD backlight PWM */
MX28_PAD_AUART1_RX__PWM_0 | MUX_CONFIG_GPIO,
MX28_PAD_AUART1_TX__PWM_1 | MUX_CONFIG_GPIO,
/* GPIO */
MX28_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D18__GPIO_1_18 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D19__GPIO_1_19 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D20__GPIO_1_20 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D21__GPIO_1_21 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D22__GPIO_1_22 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D23__GPIO_1_23 | MUX_CONFIG_GPIO,
MX28_PAD_SSP2_SS1__GPIO_2_20 | MUX_CONFIG_GPIO,
MX28_PAD_SPDIF__GPIO_3_27 | MUX_CONFIG_GPIO,
MX28_PAD_SAIF1_SDATA0__GPIO_3_26 | MUX_CONFIG_GPIO,
MX28_PAD_PWM0__GPIO_3_16 | MUX_CONFIG_GPIO,
MX28_PAD_PWM1__GPIO_3_17 | MUX_CONFIG_GPIO,
MX28_PAD_AUART0_RTS__GPIO_3_3 | MUX_CONFIG_GPIO,
MX28_PAD_AUART0_CTS__GPIO_3_2 | MUX_CONFIG_GPIO,
MX28_PAD_AUART0_TX__GPIO_3_1 | MUX_CONFIG_GPIO,
MX28_PAD_AUART0_RX__GPIO_3_0 | MUX_CONFIG_GPIO,
/* PWM */
MX28_PAD_PWM4__PWM_4 | MUX_CONFIG_GPIO,
/* SAIF0 */
MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | MUX_CONFIG_SAIF,
MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | MUX_CONFIG_SAIF,
MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | MUX_CONFIG_SAIF,
MX28_PAD_SAIF0_MCLK__SAIF0_MCLK | MUX_CONFIG_SAIF,
};
const static uint32_t lpddr_dram_vals[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 000 - 003
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 004 - 007
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 008 - 011
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 012 - 015
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 016 - 019
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 020 - 023
0x00000000, 0x00000000, 0x00010101, 0x01010101, // 024 - 027
0x000f0f01, 0x0f02010a, 0x00000000, 0x00000101, // 028 - 031
0x00000100, 0x00000100, 0x01000000, 0x00000002, // 032 - 035
0x01010000, 0x08060301, 0x06000001, 0x0a000000, // 036 - 039
0x02009c40, 0x0002030b, 0x0036a608, 0x03160305, // 040 - 043
0x03030002, 0x001f001c, 0x00000000, 0x00000000, // 044 - 047
0x00012100, 0xffff0303, 0x00012100, 0xffff0303, // 048 - 051
0x00012100, 0xffff0303, 0x00012100, 0xffff0303, // 052 - 055
0x00000003, 0x00000000, 0x00000000, 0x00000000, // 056 - 059
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 060 - 063
0x00000000, 0x00000000, 0x00000305, 0x01000f02, // 064 - 067
0x00000000, 0x00000200, 0x00020007, 0xf3004a27, // 068 - 071
0xf3004a27, 0x00000000, 0x00000000, 0x07400310, // 072 - 075
0x07400310, 0x00000000, 0x00000000, 0x00800004, // 076 - 079
0x00000000, 0x00000000, 0x01000000, 0x01020408, // 080 - 083
0x08040201, 0x000f1133, 0x00000000, 0x00001f08, // 084 - 087
0x00001f08, 0x00000000, 0x00000000, 0x00001f01, // 088 - 091
0x00001f01, 0x00000000, 0x00000000, 0x00000000, // 092 - 095
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 096 - 099
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 100 - 103
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 104 - 107
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 108 - 111
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 112 - 115
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 116 - 119
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 120 - 123
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 124 - 127
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 128 - 131
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 132 - 135
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 136 - 139
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 140 - 143
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 144 - 147
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 148 - 151
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 152 - 155
0x00000000, 0x00000000, 0x00000000, 0x00000000, // 156 - 159
0x00000000, 0x00000000, 0x00000000, 0x00010301, // 160 - 163
0x00000002, 0x00000000, 0x00000000, 0x00000000, // 164 - 167
0x00000000, 0x00000000, 0x00000000, 0x01010000, // 168 - 171
0x01000100, 0x03030000, 0x00020303, 0x01010202, // 172 - 175
0x00000000, 0x01030101, 0x21002101, 0x00030500, // 176 - 179
0x03050305, 0x00320032, 0x00320032, 0x00000000, // 180 - 183
0x00000000, 0x00000000, 0x00200020, 0x00200020, // 184 - 187
0x00000000, 0xffffffff // 188 - 189
};
void mxs_adjust_memory_params(uint32_t *dram_vals)
{
int i;
struct mxs_pinctrl_regs *pinctrl_regs =
(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
for (i = 0; i < ARRAY_SIZE(lpddr_dram_vals); i++) {
dram_vals[i] = lpddr_dram_vals[i];
}
/* Go into LPDDR mode */
writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr);
}
void board_init_ll(const uint32_t arg, const uint32_t *resptr)
{
mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
}
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