mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-16 09:43:39 +09:00
41aebf8106
Make the lowlevel_init function that these platforms have which just sets up the stack and calls a C function available to all armv7 platforms. As part of this we change some of the macros that are used to be more clear. Previously (except for am335x evm) we had been setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we should have been doing this initially and do now. Cc: Sricharan R <r.sricharan@ti.com> Tested-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@ti.com>
87 lines
2.3 KiB
C
87 lines
2.3 KiB
C
/*
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* hardware.h
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*
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* hardware specific header
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __AM33XX_HARDWARE_H
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#define __AM33XX_HARDWARE_H
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#include <asm/arch/omap.h>
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/* Module base addresses */
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#define UART0_BASE 0x44E09000
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/* DM Timer base addresses */
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#define DM_TIMER0_BASE 0x4802C000
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#define DM_TIMER1_BASE 0x4802E000
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#define DM_TIMER2_BASE 0x48040000
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#define DM_TIMER3_BASE 0x48042000
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#define DM_TIMER4_BASE 0x48044000
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#define DM_TIMER5_BASE 0x48046000
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#define DM_TIMER6_BASE 0x48048000
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#define DM_TIMER7_BASE 0x4804A000
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/* GPIO Base address */
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#define GPIO0_BASE 0x48032000
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#define GPIO1_BASE 0x4804C000
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#define GPIO2_BASE 0x481AC000
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/* BCH Error Location Module */
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#define ELM_BASE 0x48080000
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/* Watchdog Timer */
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#define WDT_BASE 0x44E35000
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/* Control Module Base Address */
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#define CTRL_BASE 0x44E10000
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#define CTRL_DEVICE_BASE 0x44E10600
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/* PRCM Base Address */
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#define PRCM_BASE 0x44E00000
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/* EMIF Base address */
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#define EMIF4_0_CFG_BASE 0x4C000000
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#define EMIF4_1_CFG_BASE 0x4D000000
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/* PLL related registers */
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#define CM_PER 0x44E00000
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#define CM_WKUP 0x44E00400
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#define CM_DPLL 0x44E00500
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#define CM_DEVICE 0x44E00700
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#define CM_CEFUSE 0x44E00A00
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#define PRM_DEVICE 0x44E00F00
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/* VTP Base address */
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#define VTP0_CTRL_ADDR 0x44E10E0C
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/* DDR Base address */
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#define DDR_CTRL_ADDR 0x44E10E04
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#define DDR_CONTROL_BASE_ADDR 0x44E11404
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#define DDR_PHY_BASE_ADDR 0x44E12000
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#define DDR_PHY_BASE_ADDR2 0x44E120A4
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/* UART */
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#define DEFAULT_UART_BASE UART0_BASE
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#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
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#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
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/* CPSW Config space */
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#define AM335X_CPSW_BASE 0x4A100000
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#define AM335X_CPSW_MDIO_BASE 0x4A101000
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#endif /* __AM33XX_HARDWARE_H */
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