mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
7a9d109b00
This is in preparation for adapting this board to function correctly on a physical MIPS Malta board. The board is moved into an "imgtec" vendor directory at the same time in order to ready us for any other boards supported by Imagination in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
70 lines
1.6 KiB
ArmAsm
70 lines
1.6 KiB
ArmAsm
/*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <config.h>
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#include <gt64120.h>
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#include <asm/addrspace.h>
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#include <asm/regdef.h>
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#include <asm/malta.h>
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#ifdef CONFIG_SYS_BIG_ENDIAN
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#define CPU_TO_GT32(_x) ((_x))
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#else
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#define CPU_TO_GT32(_x) ( \
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(((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
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(((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
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#endif
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.text
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.set noreorder
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.set mips32
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.globl lowlevel_init
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lowlevel_init:
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/*
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* Load BAR registers of GT64120 as done by YAMON
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*
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* based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
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* to the barebox mailing list.
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* The subject of the original patch:
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* 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
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* URL:
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* http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
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*
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* based on write_bootloader() in qemu.git/hw/mips_malta.c
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* see GT64120 manual and qemu.git/hw/gt64xxx.c for details
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*/
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/* move GT64120 registers from 0x14000000 to 0x1be00000 */
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li t1, KSEG1ADDR(GT_DEF_BASE)
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li t0, CPU_TO_GT32(0xdf000000)
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sw t0, GT_ISD_OFS(t1)
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/* setup MEM-to-PCI0 mapping */
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li t1, KSEG1ADDR(MALTA_GT_BASE)
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/* setup PCI0 io window to 0x18000000-0x181fffff */
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li t0, CPU_TO_GT32(0xc0000000)
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sw t0, GT_PCI0IOLD_OFS(t1)
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li t0, CPU_TO_GT32(0x40000000)
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sw t0, GT_PCI0IOHD_OFS(t1)
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/* setup PCI0 mem windows */
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li t0, CPU_TO_GT32(0x80000000)
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sw t0, GT_PCI0M0LD_OFS(t1)
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li t0, CPU_TO_GT32(0x3f000000)
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sw t0, GT_PCI0M0HD_OFS(t1)
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li t0, CPU_TO_GT32(0xc1000000)
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sw t0, GT_PCI0M1LD_OFS(t1)
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li t0, CPU_TO_GT32(0x5e000000)
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sw t0, GT_PCI0M1HD_OFS(t1)
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jr ra
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nop
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