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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
236 lines
5.6 KiB
C
236 lines
5.6 KiB
C
/*
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* Jz4740 common routines
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* Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/jz4740.h>
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void enable_interrupts(void)
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{
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}
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int disable_interrupts(void)
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{
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return 0;
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}
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/*
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* PLL output clock = EXTAL * NF / (NR * NO)
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* NF = FD + 2, NR = RD + 2
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* NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
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*/
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void pll_init(void)
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{
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struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
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register unsigned int cfcr, plcr1;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
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int nf, pllout2;
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cfcr = CPM_CPCCR_CLKOEN |
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CPM_CPCCR_PCS |
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(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
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(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
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(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
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pllout2 = (cfcr & CPM_CPCCR_PCS) ?
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CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
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/* Init USB Host clock, pllout2 must be n*48MHz */
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writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
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nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
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(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
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(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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writel(cfcr, &cpm->cpccr);
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writel(plcr1, &cpm->cppcr);
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}
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void sdram_init(void)
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{
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struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
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register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
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unsigned int cas_latency_sdmr[2] = {
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EMC_SDMR_CAS_2,
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EMC_SDMR_CAS_3,
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};
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unsigned int cas_latency_dmcr[2] = {
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1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
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2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
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};
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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cpu_clk = CONFIG_SYS_CPU_SPEED;
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mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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writel(0, &emc->bcr); /* Disable bus release */
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writew(0, &emc->rtcsr); /* Disable clock for counting */
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/* Fault DMCR value for mode register setting*/
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#define SDRAM_ROW0 11
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#define SDRAM_COL0 8
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#define SDRAM_BANK40 0
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dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
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((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
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(SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
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(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* Basic DMCR value */
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dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
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((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
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(SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
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(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* SDRAM timimg */
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ns = 1000000000 / mem_clk;
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tmp = SDRAM_TRAS / ns;
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if (tmp < 4)
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tmp = 4;
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if (tmp > 11)
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tmp = 11;
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dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
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tmp = SDRAM_RCD / ns;
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if (tmp > 3)
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tmp = 3;
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dmcr |= tmp << EMC_DMCR_RCD_BIT;
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tmp = SDRAM_TPC / ns;
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if (tmp > 7)
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tmp = 7;
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dmcr |= tmp << EMC_DMCR_TPC_BIT;
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tmp = SDRAM_TRWL / ns;
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if (tmp > 3)
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tmp = 3;
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dmcr |= tmp << EMC_DMCR_TRWL_BIT;
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tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
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if (tmp > 14)
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tmp = 14;
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dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
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/* SDRAM mode value */
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sdmode = EMC_SDMR_BT_SEQ |
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EMC_SDMR_OM_NORMAL |
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EMC_SDMR_BL_4 |
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cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
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writel(dmcr, &emc->dmcr);
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writeb(0, JZ4740_EMC_SDMR0 | sdmode);
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/* Wait for precharge, > 200us */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--)
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;
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/* Stage 2. Enable auto-refresh */
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writel(dmcr | EMC_DMCR_RFSH, &emc->dmcr);
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tmp = SDRAM_TREF / ns;
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tmp = tmp / 64 + 1;
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if (tmp > 0xff)
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tmp = 0xff;
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writew(tmp, &emc->rtcor);
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writew(0, &emc->rtcnt);
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/* Divisor is 64, CKO/64 */
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writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
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/* Wait for number of auto-refresh cycles */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--)
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;
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/* Stage 3. Mode Register Set */
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writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
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writeb(0, JZ4740_EMC_SDMR0 | sdmode);
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/* Set back to basic DMCR value */
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writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
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/* everything is ok now */
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}
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DECLARE_GLOBAL_DATA_PTR;
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void calc_clocks(void)
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{
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unsigned int pllout;
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unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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pllout = __cpm_get_pllout();
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gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
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gd->arch.sys_clk = pllout / div[__cpm_get_hdiv()];
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gd->arch.per_clk = pllout / div[__cpm_get_pdiv()];
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gd->mem_clk = pllout / div[__cpm_get_mdiv()];
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gd->arch.dev_clk = CONFIG_SYS_EXTAL;
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}
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void rtc_init(void)
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{
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struct jz4740_rtc *rtc = (struct jz4740_rtc *)JZ4740_RTC_BASE;
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while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
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;
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writel(readl(&rtc->rcr) | RTC_RCR_AE, &rtc->rcr); /* enable alarm */
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while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
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;
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writel(0x00007fff, &rtc->rgr); /* type value */
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while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
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;
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writel(0x0000ffe0, &rtc->hwfcr); /* Power on delay 2s */
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while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
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;
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writel(0x00000fe0, &rtc->hrcr); /* reset delay 125ms */
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}
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/* U-Boot common routines */
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phys_size_t initdram(int board_type)
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{
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struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
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u32 dmcr;
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u32 rows, cols, dw, banks;
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ulong size;
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dmcr = readl(&emc->dmcr);
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rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
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cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
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dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
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banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
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size = (1 << (rows + cols)) * dw * banks;
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return size;
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}
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