mirror of
https://github.com/brain-hackers/u-boot-brain
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ddf56bc7e3
Many System on Chip(SoC) solutions are complex with multiple processors on the same die dedicated to either general purpose of specialized functions. Many examples do exist in today's SoCs from various vendors. Typical examples are micro controllers such as an ARM M3/M0 doing a offload of specific function such as event integration or power management or controlling camera etc. Traditionally, the responsibility of loading up such a processor with a firmware and communication has been with a High Level Operating System(HLOS) such as Linux. However, there exists classes of products where Linux would need to expect services from such a processor or the delay of Linux and operating system being able to load up such a firmware is unacceptable. To address these needs, we need some minimal capability to load such a system and ensure it is started prior to an Operating System(Linux or any other) is started up. NOTE: This is NOT meant to be a solve-all solution, instead, it tries to address certain class of SoCs and products that need such a solution. A very simple model is introduced here as part of the initial support that supports microcontrollers with internal memory (no MMU, no execution from external memory, or specific image format needs). This basic framework can then (hopefully) be extensible to other complex SoC processor support as need be. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
71 lines
2.4 KiB
C
71 lines
2.4 KiB
C
/*
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* Copyright (c) 2013 Google, Inc
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*
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* (C) Copyright 2012
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* Pavel Herrmann <morpheus.ibis@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DM_UCLASS_ID_H
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#define _DM_UCLASS_ID_H
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/* TODO(sjg@chromium.org): this could be compile-time generated */
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enum uclass_id {
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/* These are used internally by driver model */
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UCLASS_ROOT = 0,
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UCLASS_DEMO,
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UCLASS_TEST,
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UCLASS_TEST_FDT,
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UCLASS_TEST_BUS,
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UCLASS_SPI_EMUL, /* sandbox SPI device emulator */
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UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
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UCLASS_PCI_EMUL, /* sandbox PCI device emulator */
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UCLASS_USB_EMUL, /* sandbox USB bus device emulator */
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UCLASS_SIMPLE_BUS, /* bus with child devices */
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/* U-Boot uclasses start here - in alphabetical order */
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UCLASS_CLK, /* Clock source, e.g. used by peripherals */
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UCLASS_CPU, /* CPU, typically part of an SoC */
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UCLASS_CROS_EC, /* Chrome OS EC */
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UCLASS_DISPLAY_PORT, /* Display port video */
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UCLASS_RAM, /* RAM controller */
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UCLASS_ETH, /* Ethernet device */
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UCLASS_GPIO, /* Bank of general-purpose I/O pins */
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UCLASS_I2C, /* I2C bus */
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UCLASS_I2C_EEPROM, /* I2C EEPROM device */
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UCLASS_I2C_GENERIC, /* Generic I2C device */
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UCLASS_I2C_MUX, /* I2C multiplexer */
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UCLASS_LED, /* Light-emitting diode (LED) */
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UCLASS_LPC, /* x86 'low pin count' interface */
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UCLASS_MASS_STORAGE, /* Mass storage device */
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UCLASS_MMC, /* SD / MMC card or chip */
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UCLASS_MOD_EXP, /* RSA Mod Exp device */
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UCLASS_PCH, /* x86 platform controller hub */
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UCLASS_PCI, /* PCI bus */
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UCLASS_PCI_GENERIC, /* Generic PCI bus device */
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UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
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UCLASS_PINCONFIG, /* Pin configuration node device */
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UCLASS_PMIC, /* PMIC I/O device */
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UCLASS_REGULATOR, /* Regulator device */
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UCLASS_RESET, /* Reset device */
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UCLASS_REMOTEPROC, /* Remote Processor device */
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UCLASS_RTC, /* Real time clock device */
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UCLASS_SERIAL, /* Serial UART */
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UCLASS_SPI, /* SPI bus */
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UCLASS_SPI_FLASH, /* SPI flash */
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UCLASS_SPI_GENERIC, /* Generic SPI flash target */
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UCLASS_SYSCON, /* System configuration device */
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UCLASS_THERMAL, /* Thermal sensor */
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UCLASS_TPM, /* Trusted Platform Module TIS interface */
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UCLASS_USB, /* USB bus */
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UCLASS_USB_DEV_GENERIC, /* USB generic device */
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UCLASS_USB_HUB, /* USB hub */
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UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */
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UCLASS_COUNT,
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UCLASS_INVALID = -1,
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};
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#endif
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