mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ba8e76bd49
Use the 'video-mode' environment variable (for Freescale chips that have a DIU display controller) to designate the full video configuration. Previously, the DIU driver used the 'monitor' variable, and it was used only to determine the output video port. The old definition of the "monitor" environment variable only determines which video port to use for output. This variable was set to a number (0, 1, or sometimes 2) to specify a DVI, LVDS, or Dual-LVDS port. The resolution was hard-coded into board-specific code. The Linux command-line arguments needed to be hard-coded to the proper video definition string. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
479 lines
14 KiB
C
479 lines
14 KiB
C
/*
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* (C) Copyright 2009-2010
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* Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* pdm360ng board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_PDM360NG 1
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/*
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* Memory map for the PDM360NG board:
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*
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* 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB)
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* 0x2000_0000 - 0x3FFF_FFFF reserved (DDR RAM (512 MB)
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* 0x5000_0000 - 0x5001_FFFF SRAM (128 KB)
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* 0x5004_0000 - 0x5005_FFFF MRAM (CS2) (128 KB)
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* 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
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* 0xF000_0000 - 0xF7FF_FFFF NOR FLASH (CS0) (128 MB)
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* 0xF800_0000 - 0xFFFF_FFFF NOR FLASH (CS1) (128 MB) optional
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*/
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_MPC512X 1 /* MPC512X family */
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#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
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#define CONFIG_SYS_TEXT_BASE 0xF0000000
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/* Used for silent command in environment */
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#define CONFIG_SYS_DEVICE_NULLDEV
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#define CONFIG_SILENT_CONSOLE
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/* Video */
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#define CONFIG_VIDEO
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#if defined(CONFIG_VIDEO)
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_RLE8
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#endif
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#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_IMMR 0x80000000
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#define CONFIG_SYS_DIU_ADDR ((CONFIG_SYS_IMMR) + 0x2100)
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/*
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* DDR Setup
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*/
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/* DDR is system memory */
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#define CONFIG_SYS_DDR_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000
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/* DDR pin mux and slew rate */
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#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000012
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/* Manually set all parameters as there's no SPD etc. */
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/*
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* DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
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*
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* SYS_CFG:
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* [31:31] MDDRC Soft Reset: Diabled
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* [30:30] DRAM CKE pin: Enabled
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* [29:29] DRAM CLK: Enabled
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* [28:28] Command Mode: Enabled (For initialization only)
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* [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
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* [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
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* [20:19] Read Test: DON'T USE
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* [18:18] Self Refresh: Enabled
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* [17:17] 16bit Mode: Disabled
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* [16:13] Read Delay: 3
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* [12:12] Half DQS Delay: Disabled
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* [11:11] Quarter DQS Delay: Disabled
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* [10:08] Write Delay: 2
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* [07:07] Early ODT: Disabled
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* [06:06] On DIE Termination: Enabled
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* [05:05] FIFO Overflow Clear: DON'T USE here
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* [04:04] FIFO Underflow Clear: DON'T USE here
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* [03:03] FIFO Overflow Pending: DON'T USE here
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* [02:02] FIFO Underlfow Pending: DON'T USE here
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* [01:01] FIFO Overlfow Enabled: Enabled
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* [00:00] FIFO Underflow Enabled: Enabled
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* TIME_CFG0
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* [31:16] DRAM Refresh Time: 0 CSB clocks
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* [15:8] DRAM Command Time: 0 CSB clocks
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* [07:00] DRAM Precharge Time: 0 CSB clocks
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* TIME_CFG1
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* [31:26] DRAM tRFC:
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* [25:21] DRAM tWR1:
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* [20:17] DRAM tWRT1:
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* [16:11] DRAM tDRR:
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* [10:05] DRAM tRC:
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* [04:00] DRAM tRAS:
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* TIME_CFG2
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* [31:28] DRAM tRCD:
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* [27:23] DRAM tFAW:
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* [22:19] DRAM tRTW1:
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* [18:15] DRAM tCCD:
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* [14:10] DRAM tRTP:
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* [09:05] DRAM tRP:
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* [04:00] DRAM tRPA
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*/
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#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A40
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#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
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#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
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#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
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/*
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* Alternative 1: small RAM (128 MB) configuration
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*/
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#define CONFIG_SYS_MDDRC_SYS_CFG_ALT1 0xE8604A40
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#define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E
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#define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168
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#define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863
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#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
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#define CONFIG_SYS_DDRCMD_NOP 0x01380000
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#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
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#define CONFIG_SYS_DDRCMD_EM2 0x01020000 /* EMR2 */
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#define CONFIG_SYS_DDRCMD_EM3 0x01030000 /* EMR3 */
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/* EMR with 150 ohm ODT todo: verify */
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#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010040
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#define CONFIG_SYS_DDRCMD_RES_DLL 0x01000100
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#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
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#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
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/* EMR with 150 ohm ODT todo: verify */
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#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x010107C0
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/* EMR new command with 150 ohm ODT todo: verify */
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#define CONFIG_SYS_DDRCMD_OCD_EXIT 0x01010440
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/* DDR Priority Manager Configuration */
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#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
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#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
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#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
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#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
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#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
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#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
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#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
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#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
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#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
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#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
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#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
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#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
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#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
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#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
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#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
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#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
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#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
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/*
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* NOR FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_BASE 0xF0000000 /* start of FLASH-Bank0 */
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#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max size of a Bank */
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/* start of FLASH-Bank1 */
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#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_FLASH_BASE + \
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CONFIG_SYS_FLASH_SIZE)
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST \
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{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
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#define CONFIG_SYS_SRAM_BASE 0x50000000
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#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
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/* ALE active low, data size 4 bytes */
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#define CONFIG_SYS_CS0_CFG 0x05059350
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/* ALE active low, data size 4 bytes */
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#define CONFIG_SYS_CS1_CFG 0x05059350
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#define CONFIG_SYS_MRAM_BASE 0x50040000
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#define CONFIG_SYS_MRAM_SIZE 0x00020000
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/* ALE active low, data size 4 bytes */
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#define CONFIG_SYS_CS2_CFG 0x05059110
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/* alt. CS timing for CS0, CS1, CS2 */
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#define CONFIG_SYS_CS_ALETIMING 0x00000007
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/*
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* NAND FLASH
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*/
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#define CONFIG_CMD_NAND /* enable NAND support */
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#define CONFIG_NAND_MPC5121_NFC
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
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#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
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/*
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* Configuration parameters for MPC5121 NAND driver
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*/
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#define CONFIG_FSL_NFC_WIDTH 1
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#define CONFIG_FSL_NFC_WRITE_SIZE 2048
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#define CONFIG_FSL_NFC_SPARE_SIZE 64
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#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
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/*
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* Dynamic MTD partition support
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*/
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define CONFIG_FLASH_CFI_MTD
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#define MTDIDS_DEFAULT "nor0=f0000000.flash,nor1=f8000000.flash," \
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"nand0=MPC5121 NAND"
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/*
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* Flash layout
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*/
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#define MTDPARTS_DEFAULT "mtdparts=f0000000.flash:512k(u-boot)," \
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"256k(environment1)," \
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"256k(environment2)," \
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"256k(splash-factory)," \
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"2m(FIT: recovery)," \
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"4608k(fs-recovery)," \
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"256k(splash-customer),"\
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"5m(FIT: kernel+dtb)," \
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"64m(rootfs squash)ro," \
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"51m(userfs ubi);" \
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"f8000000.flash:-(unused);" \
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"MPC5121 NAND:1024m(extended-userfs)"
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/*
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* Override partitions in device tree using info
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* in "mtdparts" environment variable
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*/
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#ifdef CONFIG_CMD_MTDPARTS
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#define CONFIG_FDT_FIXUP_PARTITIONS
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#endif
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* 512 kB for monitor */
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#ifdef CONFIG_FSL_DIU_FB
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#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* for malloc */
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#else
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
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#endif
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
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#if CONFIG_PSC_CONSOLE != 6
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#error CONFIG_PSC_CONSOLE must be 6
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#endif
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#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC6_TX_SIZE
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#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC6_TX_ADDR
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#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE
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#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR
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/*
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* Used PSC UART devices
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*/
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#define CONFIG_SERIAL_MULTI
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#define CONFIG_SYS_PSC1
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#define CONFIG_SYS_PSC4
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#define CONFIG_SYS_PSC6
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/*
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* Co-processor communication parameters
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*/
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#define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY 5000
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#define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE 38400
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/*
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* I2C
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*/
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_CMD_TREE
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/* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM addr */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* ST AT24C01 */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-Byte Write Mode */
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/*
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* MAC addr in EEPROM
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*/
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#define CONFIG_SYS_I2C_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET 0x10
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/*
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* Enabled only to delete "ethaddr" before testing
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* "ethaddr" setting from EEPROM
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*/
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#define CONFIG_ENV_OVERWRITE
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC512x_FEC 1
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#define CONFIG_NET_MULTI
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#define CONFIG_PHY_ADDR 0x1F
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_FEC_AN_TIMEOUT 1
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#define CONFIG_HAS_ETH0
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/*
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* Configure on-board RTC
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*/
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#define CONFIG_RTC_M41T62 /* use M41T00 rtc via i2c */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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/* This has to be a multiple of the Flash sector size */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#ifdef CONFIG_VIDEO
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#define CONFIG_CMD_BMP
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Max number of command args */
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#define CONFIG_SYS_MAXARGS 16
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* Decrementer freq: 1ms ticks */
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#define CONFIG_SYS_HZ 1000
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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/* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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/* Cache Configuration */
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#define CONFIG_SYS_DCACHE_SIZE 32768
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#ifdef CONFIG_CMD_KGDB
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/* log base 2 of the above value */
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#define CONFIG_SYS_CACHELINE_SHIFT 5
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#endif
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
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#define CONFIG_SYS_HID2 HID2_HBE
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#ifdef CONFIG_SERIAL_MULTI
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/* POST support */
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#define CONFIG_POST (CONFIG_SYS_POST_COPROC)
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#endif
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/*
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* Environment Configuration
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*/
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#define CONFIG_TIMESTAMP
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#define CONFIG_HOSTNAME pdm360ng
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 400000
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#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
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#define CONFIG_PREBOOT "echo;" \
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"echo PDM360NG SAMPLE;" \
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"echo"
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#define CONFIG_BOOTCOMMAND "run env_cont"
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
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#define CONFIG_FIT
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|
#define CONFIG_FIT_VERBOSE
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|
|
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#define OF_CPU "PowerPC,5121@0"
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#define OF_SOC_COMPAT "fsl,mpc5121-immr"
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#define OF_TBCLK (bd->bi_busfreq / 4)
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|
#define OF_STDOUT_PATH "/soc@80000000/serial@11600"
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|
|
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/*
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* Include common options for all mpc5121 boards
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|
*/
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|
#include "mpc5121-common.h"
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|
|
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#endif /* __CONFIG_H */
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