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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
357 lines
12 KiB
C
357 lines
12 KiB
C
/*
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* A collection of structures, addresses, and values associated with
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* the Motorola 860T FADS board. Copied from the MBX stuff.
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* Magnus Damm added defines for 8xxrom and extended bd_info.
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* Helmut Buchsbaum added bitvalues for BCSRx
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*
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
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*/
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/*
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* The GENIETV is using the following physical memorymap (copied from
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* the FADS configuration):
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*
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* ff020000 -> ff02ffff : pcmcia
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* ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM
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* ff000000 -> ff00ffff : IMAP internal in the cpu
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* 30000000 -> 300fffff : flash connected to CS0
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* 00000000 -> nnnnnnnn : sdram setup by U-Boot
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*
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* CS pins are connected as follows:
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*
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* CS0 -512Kb boot flash
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* CS1 - SDRAM #1
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* CS2 - SDRAM #2
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* CS3 - Flash #1
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* CS4 - Flash #2
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* CS5 - Lon (if present)
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* CS6 - PCMCIA #1
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* CS7 - PCMCIA #2
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
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#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
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#define CONFIG_SYS_ALLOC_DPRAM /* Use dynamic DPRAM allocation */
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#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
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/*#define CONFIG_VIDEO 1 / To enable the video initialization */
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/*#define CONFIG_VIDEO_ADDR 0x00200000 */
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/*#define CONFIG_HARD_I2C 1 / I2C with hardware support */
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/*#define CONFIG_PCMCIA 1 / To enable the PCMCIA initialization */
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/*#define CONFIG_SYS_PCMCIA_IO_ADDR 0xff020000 */
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/*#define CONFIG_SYS_PCMCIA_IO_SIZE 0x10000 */
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/*#define CONFIG_SYS_PCMCIA_MEM_ADDR 0xe0000000 */
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/*#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000 */
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/* Video related */
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/*#define CONFIG_VIDEO_LOGO 1 / Show the logo */
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/*#define CONFIG_VIDEO_ENCODER_AD7177 1 / Enable this encoder */
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/*#define CONFIG_VIDEO_ENCODER_AD7177_ADDR 0xF4 / ALSB to ground */
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/* Wireless 56Khz 4PPM keyboard on SMCx */
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/*#define CONFIG_KEYBOARD 0 */
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/*#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 / SMC to use (0 indexed) */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#include <mpc8xx_irq.h>
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#define CONFIG_GENIETV 1
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#define CONFIG_MPC823 1
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 9600
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#define MPC8XX_FACT 12 /* Multiply by 12 */
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#define MPC8XX_XIN 5000000 /* 4 MHz clock */
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#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
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#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20)
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#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#if 1
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#define CONFIG_BOOTDELAY 1 /* autoboot after 2 seconds */
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#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
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#define CONFIG_BOOTARGS ""
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#define CONFIG_BOOTCOMMAND \
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"bootp; tftp; " \
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"setenv bootargs console=tty0 console=ttyS0 " \
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"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \
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"bootm "
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#else
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#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xFF000000
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#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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* Also NOTE that it doesn't mean SDRAM - it means MEMORY.
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0x02800000
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#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
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#if 0
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
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#else
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#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
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#endif
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
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#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/
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/* values according to the manual */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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*/
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer *
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* interrupt status bit - leave PLL multiplication factor unchanged !
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*
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* #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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*/
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#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CONFIG_SYS_SCCR (SCCR_TBS | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_DER 0
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/* Because of the way the 860 starts up and assigns CS0 the
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* entire address space, we have to set the memory controller
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* differently. Normally, you write the option register
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* first, and then enable the chip select by writing the
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* base register. For CS0, you must write the base register
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* first, followed by the option register.
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*/
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/*
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* Init Memory Controller:
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*
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* BR0 and OR0(FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
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#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask (512Kb) */
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/* FLASH timing */
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
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OR_SCY_15_CLK | OR_TRLX )
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/*#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) */
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 0xfff80ff4 */
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#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */
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/*
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* BR1/2 and OR1/2 (SDRAM)
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*/
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#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
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#define SDRAM_MAX_SIZE 0x04000000 /* 64Mb bank */
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#define SDRAM_BASE1_PRELIM 0x00000000 /* First bank */
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#define SDRAM_BASE2_PRELIM 0x10000000 /* Second bank */
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/*
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* Memory Periodic Timer Prescaler
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*/
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/* periodic timer for refresh */
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#define CONFIG_SYS_MBMR_PTB 0x5d /* start with divider for 100 MHz */
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/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
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#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
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#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32
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/*
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* MBMR settings for SDRAM
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*/
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/* 8 column SDRAM */
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#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \
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| MAMR_TLFA_4X) /* 0x5d802114 */
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/* values according to the manual */
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#define CONFIG_DRAM_50MHZ 1
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#define CONFIG_SDRAM_50MHZ
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/* We don't use the 8259.
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*/
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#define NR_8259_INTS 0
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/*
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* MPC8xx CPM Options
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*/
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#define CONFIG_SCC_ENET 1
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#define CONFIG_DISK_SPINUP_TIME 1000000
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/* PCMCIA configuration */
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#define PCMCIA_MAX_SLOTS 1
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#define PCMCIA_SLOT_B 1
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#endif /* __CONFIG_H */
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