mirror of
https://github.com/brain-hackers/u-boot-brain
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323d1f9d5b
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled. Each SoC has its own defconfig file
for the build-test coverage. Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.
Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture. In fact, some
SoCs of UniPhier family are very similar:
- PH1-LD4 and PH1-sLD8
- PH1-LD6b and ProXstream2 (will be added in the upcoming commit)
This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
50 lines
1.7 KiB
C
50 lines
1.7 KiB
C
/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/io.h>
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#include <mach/init.h>
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#include <mach/sg-regs.h>
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void ph1_ld4_pin_init(void)
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{
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u32 tmp;
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/* Comment format: PAD Name -> Function Name */
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#ifdef CONFIG_NAND_DENALI
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sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */
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sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */
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sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */
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sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */
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sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */
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sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */
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sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */
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sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */
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sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */
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sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */
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sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */
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sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */
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sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */
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sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */
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sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */
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sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */
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sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
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#endif
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#ifdef CONFIG_USB_EHCI_UNIPHIER
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sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
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sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */
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sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
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sg_set_pinsel(56, 0, 8, 4); /* USB1OD -> USB1OD */
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/* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */
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/* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */
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#endif
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tmp = readl(SG_IECTRL);
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tmp |= 0x41;
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writel(tmp, SG_IECTRL);
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}
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