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https://github.com/brain-hackers/u-boot-brain
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21ff7344d1
Convert cache flush to use dm cpu data.
The original cache flush functions are written in assembly
and use CONFIG_SYS_{I,D}CACHE_SIZE... macros. It is difficult
to convert to use cache configuration in dm cpu data which is
extracted from device tree.
The cacheflush.c of Linux nios2 arch uses cpuinfo structure,
which is very close to our dm cpu data. So we copy and modify
it to arch/nios2/lib/cache.c to replace the old cache.S.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
19 lines
438 B
C
19 lines
438 B
C
/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_NIOS2_CACHE_H_
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#define __ASM_NIOS2_CACHE_H_
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/*
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* Valid L1 data cache line sizes for the NIOS2 architecture are 4,
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* 16, and 32 bytes. We default to the largest of these values for
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* alignment of DMA buffers.
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*/
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#define ARCH_DMA_MINALIGN 32
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#endif /* __ASM_NIOS2_CACHE_H_ */
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