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7a25a63c13
u-boot-brain/drivers/clk/rockchip
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Xu Ziyuan 7a25a63c13 rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO 
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
..
clk_rk3036.c rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO 2017-05-10 13:37:21 -06:00
clk_rk3188.c rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO 2017-05-10 13:37:21 -06:00
clk_rk3288.c rockchip: clk: rk3288: limit gpll and cpll init to SPL build 2017-03-16 16:03:44 -06:00
clk_rk3328.c rockchip: rk3328: add clock driver 2017-03-16 16:03:46 -06:00
clk_rk3399.c rockchip: clk: rk3399: 24MHz is not a power of 2 2017-04-04 20:01:57 -06:00
Makefile rockchip: rk3328: add clock driver 2017-03-16 16:03:46 -06:00