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u-boot-brain/drivers/clk/rockchip
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Kever Yang 1960b01034 rockchip: clock: rk3036: some fix according TRM 
- hclk/pclk_div range　should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:20 -06:00
..
clk_rk3036.c rockchip: clock: rk3036: some fix according TRM 2017-06-07 07:29:20 -06:00
clk_rk3188.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rk3288.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rk3328.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rk3368.c rockchip: rk3368: Add clock driver 2017-06-07 07:29:19 -06:00
clk_rk3399.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
Makefile rockchip: rk3368: Add clock driver 2017-06-07 07:29:19 -06:00