mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 03:49:43 +09:00
79f2b3992f
Calculate the early uart clock from the system clock registers set by the bootrom other than the predefine uboot clock macros. Split the early baudrate setting function and the normal baudrate setting one. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
138 lines
2.4 KiB
C
138 lines
2.4 KiB
C
/*
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* clocks.c - figure out sclk/cclk/vco and such
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <asm/clock.h>
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/* Get the voltage input multiplier */
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u_long get_vco(void)
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{
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static u_long cached_vco_pll_ctl, cached_vco;
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u_long msel, pll_ctl;
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pll_ctl = bfin_read_PLL_CTL();
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if (pll_ctl == cached_vco_pll_ctl)
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return cached_vco;
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else
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cached_vco_pll_ctl = pll_ctl;
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msel = (pll_ctl & MSEL) >> MSEL_P;
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if (0 == msel)
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msel = (MSEL >> MSEL_P) + 1;
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cached_vco = CONFIG_CLKIN_HZ;
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cached_vco >>= (pll_ctl & DF);
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cached_vco *= msel;
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return cached_vco;
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}
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/* Get the Core clock */
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u_long get_cclk(void)
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{
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static u_long cached_cclk_pll_div, cached_cclk;
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u_long div, csel, ssel;
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if (pll_is_bypassed())
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return CONFIG_CLKIN_HZ;
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div = bfin_read_PLL_DIV();
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if (div == cached_cclk_pll_div)
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return cached_cclk;
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else
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cached_cclk_pll_div = div;
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csel = (div & CSEL) >> CSEL_P;
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#ifndef CGU_DIV
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ssel = (div & SSEL) >> SSEL_P;
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if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
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cached_cclk = get_vco() / ssel;
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else
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cached_cclk = get_vco() >> csel;
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#else
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cached_cclk = get_vco() / csel;
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#endif
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return cached_cclk;
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}
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/* Get the System clock */
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#ifdef CGU_DIV
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static u_long cached_sclk_pll_div, cached_sclk;
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static u_long cached_sclk0, cached_sclk1, cached_dclk;
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static u_long _get_sclk(u_long *cache)
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{
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u_long div, ssel;
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if (pll_is_bypassed())
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return CONFIG_CLKIN_HZ;
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div = bfin_read_PLL_DIV();
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if (div == cached_sclk_pll_div)
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return *cache;
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else
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cached_sclk_pll_div = div;
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ssel = (div & SYSSEL) >> SYSSEL_P;
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cached_sclk = get_vco() / ssel;
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ssel = (div & S0SEL) >> S0SEL_P;
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cached_sclk0 = cached_sclk / ssel;
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ssel = (div & S1SEL) >> S1SEL_P;
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cached_sclk1 = cached_sclk / ssel;
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ssel = (div & DSEL) >> DSEL_P;
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cached_dclk = get_vco() / ssel;
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return *cache;
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}
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u_long get_sclk(void)
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{
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return _get_sclk(&cached_sclk);
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}
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u_long get_sclk0(void)
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{
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return _get_sclk(&cached_sclk0);
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}
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u_long get_sclk1(void)
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{
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return _get_sclk(&cached_sclk1);
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}
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u_long get_dclk(void)
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{
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return _get_sclk(&cached_dclk);
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}
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#else
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u_long get_sclk(void)
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{
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static u_long cached_sclk_pll_div, cached_sclk;
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u_long div, ssel;
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if (pll_is_bypassed())
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return CONFIG_CLKIN_HZ;
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div = bfin_read_PLL_DIV();
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if (div == cached_sclk_pll_div)
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return cached_sclk;
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else
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cached_sclk_pll_div = div;
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ssel = (div & SSEL) >> SSEL_P;
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cached_sclk = get_vco() / ssel;
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return cached_sclk;
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}
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#endif
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