mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 11:59:46 +09:00
79f2b3992f
Calculate the early uart clock from the system clock registers set by the bootrom other than the predefine uboot clock macros. Split the early baudrate setting function and the normal baudrate setting one. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
75 lines
1.5 KiB
C
75 lines
1.5 KiB
C
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/*
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* Copyright (C) 2012 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __CLOCK_H__
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#define __CLOCK_H__
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#include <asm/blackfin.h>
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#ifdef PLL_CTL
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#include <asm/mach-common/bits/pll.h>
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# define pll_is_bypassed() (bfin_read_PLL_STAT() & DF)
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#else
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#include <asm/mach-common/bits/cgu.h>
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# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP)
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# define bfin_read_PLL_CTL() bfin_read_CGU_CTL()
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# define bfin_read_PLL_DIV() bfin_read_CGU_DIV()
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# define SSEL SYSSEL
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# define SSEL_P SYSSEL_P
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#endif
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__attribute__((always_inline))
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static inline uint32_t early_division(uint32_t dividend, uint32_t divisor)
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{
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uint32_t quotient;
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uint32_t i, j;
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for (quotient = 1, i = 1; dividend > divisor; ++i) {
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j = divisor << i;
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if (j > dividend || (j & 0x80000000)) {
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--i;
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quotient += (1 << i);
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dividend -= (divisor << i);
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i = 0;
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}
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}
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return quotient;
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}
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__attribute__((always_inline))
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static inline uint32_t early_get_uart_clk(void)
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{
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uint32_t msel, pll_ctl, vco;
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uint32_t div, ssel, sclk, uclk;
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pll_ctl = bfin_read_PLL_CTL();
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msel = (pll_ctl & MSEL) >> MSEL_P;
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if (msel == 0)
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msel = (MSEL >> MSEL_P) + 1;
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vco = (CONFIG_CLKIN_HZ >> (pll_ctl & DF)) * msel;
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sclk = vco;
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if (!pll_is_bypassed()) {
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div = bfin_read_PLL_DIV();
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ssel = (div & SSEL) >> SSEL_P;
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sclk = early_division(vco, ssel);
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}
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uclk = sclk;
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#ifdef CGU_DIV
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ssel = (div & S0SEL) >> S0SEL_P;
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uclk = early_division(sclk, ssel);
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#endif
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return uclk;
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}
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#ifdef CGU_DIV
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# define get_uart_clk get_sclk0
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#else
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# define get_uart_clk get_sclk
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#endif
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#endif
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