Kumar Gala 79e4e6480b powerpc/8xxx: Enabled hwconfig for memory interleaving ... Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with hwconfig parameters. The syntax is setenv hwconfig "fsl_ddr:ctlr_intlv=<mode>,bank_intlv=<mode>" The mode values for memory controller interleaving are cacheline page bank superbank The mode values for bank interleaving are cs0_cs1 cs2_cs3 cs0_cs1_and_cs2_cs3 cs0_cs1_cs2_cs3 Signed-off-by: York Sun <yorksun@freescale.com>		2010-07-26 13:16:08 -05:00
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ddr	powerpc/8xxx: Enabled hwconfig for memory interleaving	2010-07-26 13:16:08 -05:00
cpu.c	powerpc/p3041: Add various p3041 related defines	2010-07-20 04:41:19 -05:00
fdt.c	powerpc/8xxx: Add is_core_disabled to remove disabled cores from dtb	2010-07-16 10:55:08 -05:00
fsl_lbc.c	powerpc 83xx/85xx: Merge lbc upmconfig code	2010-07-16 10:55:09 -05:00
Makefile	83xx/85xx/86xx: LBC register cleanup	2010-07-16 10:55:09 -05:00
pci_cfg.c	85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled	2010-05-12 04:53:51 -05:00