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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
372 lines
9.0 KiB
C
372 lines
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010 - 2011
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/emc.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/sdram_param.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/apb_misc.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/fuse.h>
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#include <asm/arch-tegra/warmboot.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_TEGRA_CLOCK_SCALING
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#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
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#endif
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/*
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* This is the place in SRAM where the SDRAM parameters are stored. There
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* are 4 blocks, one for each RAM code
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*/
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#define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
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/* TODO: If we later add support for the Misc GP controller, refactor this */
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union xm2cfga_reg {
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struct {
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u32 reserved0:2;
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u32 hsm_en:1;
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u32 reserved1:2;
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u32 preemp_en:1;
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u32 vref_en:1;
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u32 reserved2:5;
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u32 cal_drvdn:5;
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u32 reserved3:3;
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u32 cal_drvup:5;
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u32 reserved4:3;
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u32 cal_drvdn_slwr:2;
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u32 cal_drvup_slwf:2;
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};
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u32 word;
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};
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union xm2cfgd_reg {
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struct {
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u32 reserved0:2;
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u32 hsm_en:1;
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u32 schmt_en:1;
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u32 lpmd:2;
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u32 vref_en:1;
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u32 reserved1:5;
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u32 cal_drvdn:5;
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u32 reserved2:3;
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u32 cal_drvup:5;
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u32 reserved3:3;
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u32 cal_drvdn_slwr:2;
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u32 cal_drvup_slwf:2;
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};
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u32 word;
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};
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/*
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* TODO: This register is not documented in the TRM yet. We could move this
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* into the EMC and give it a proper interface, but not while it is
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* undocumented.
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*/
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union fbio_spare_reg {
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struct {
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u32 reserved:24;
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u32 cfg_wb0:8;
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};
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u32 word;
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};
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/* We pack the resume information into these unions for later */
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union scratch2_reg {
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struct {
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u32 pllm_base_divm:5;
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u32 pllm_base_divn:10;
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u32 pllm_base_divp:3;
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u32 pllm_misc_lfcon:4;
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u32 pllm_misc_cpcon:4;
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u32 gp_xm2cfga_padctrl_preemp:1;
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u32 gp_xm2cfgd_padctrl_schmt:1;
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u32 osc_ctrl_xobp:1;
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u32 memory_type:3;
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};
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u32 word;
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};
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union scratch4_reg {
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struct {
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u32 emc_clock_divider:8;
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u32 pllm_stable_time:8;
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u32 pllx_stable_time:8;
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u32 emc_fbio_spare_cfg_wb0:8;
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};
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u32 word;
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};
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union scratch24_reg {
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struct {
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u32 emc_auto_cal_wait:8;
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u32 emc_pin_program_wait:8;
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u32 warmboot_wait:8;
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u32 reserved:8;
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};
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u32 word;
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};
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int warmboot_save_sdram_params(void)
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{
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u32 ram_code;
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struct sdram_params sdram;
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struct apb_misc_pp_ctlr *apb_misc =
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(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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struct apb_misc_gp_ctlr *gp =
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(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
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struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
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union scratch2_reg scratch2;
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union scratch4_reg scratch4;
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union scratch24_reg scratch24;
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union xm2cfga_reg xm2cfga;
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union xm2cfgd_reg xm2cfgd;
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union fbio_spare_reg fbio_spare;
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/* get ram code that is used as index to array sdram_params in BCT */
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ram_code = (readl(&apb_misc->strapping_opt_a) >>
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STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
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memcpy(&sdram,
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(char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
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sizeof(sdram));
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xm2cfga.word = readl(&gp->xm2cfga);
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xm2cfgd.word = readl(&gp->xm2cfgd);
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scratch2.word = 0;
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scratch2.osc_ctrl_xobp = clock_get_osc_bypass();
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/* Get the memory PLL settings */
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{
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u32 divm, divn, divp, cpcon, lfcon;
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if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
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&cpcon, &lfcon))
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return -1;
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scratch2.pllm_base_divm = divm;
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scratch2.pllm_base_divn = divn;
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scratch2.pllm_base_divp = divp;
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scratch2.pllm_misc_cpcon = cpcon;
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scratch2.pllm_misc_lfcon = lfcon;
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}
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scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en;
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scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en;
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scratch2.memory_type = sdram.memory_type;
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writel(scratch2.word, &pmc->pmc_scratch2);
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/* collect data from various sources for pmc_scratch4 */
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fbio_spare.word = readl(&emc->fbio_spare);
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scratch4.word = 0;
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scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0;
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scratch4.emc_clock_divider = sdram.emc_clock_divider;
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scratch4.pllm_stable_time = -1;
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scratch4.pllx_stable_time = -1;
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writel(scratch4.word, &pmc->pmc_scratch4);
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/* collect various data from sdram for pmc_scratch24 */
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scratch24.word = 0;
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scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait;
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scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait;
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scratch24.warmboot_wait = sdram.warm_boot_wait;
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writel(scratch24.word, &pmc->pmc_scratch24);
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return 0;
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}
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static u32 get_major_version(void)
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{
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u32 major_id;
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struct apb_misc_gp_ctlr *gp =
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(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
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major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
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HIDREV_MAJORPREV_SHIFT;
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return major_id;
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}
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static int is_production_mode_fuse_set(struct fuse_regs *fuse)
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{
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return readl(&fuse->production_mode);
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}
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static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse)
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{
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return readl(&fuse->security_mode);
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}
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static int is_failure_analysis_mode(struct fuse_regs *fuse)
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{
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return readl(&fuse->fa);
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}
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static int ap20_is_odm_production_mode(void)
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{
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struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
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if (!is_failure_analysis_mode(fuse) &&
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is_odm_production_mode_fuse_set(fuse))
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return 1;
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else
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return 0;
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}
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static int ap20_is_production_mode(void)
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{
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struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
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if (get_major_version() == 0)
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return 1;
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if (!is_failure_analysis_mode(fuse) &&
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is_production_mode_fuse_set(fuse) &&
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!is_odm_production_mode_fuse_set(fuse))
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return 1;
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else
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return 0;
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}
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static enum fuse_operating_mode fuse_get_operation_mode(void)
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{
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u32 chip_id;
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struct apb_misc_gp_ctlr *gp =
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(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
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chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
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HIDREV_CHIPID_SHIFT;
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if (chip_id == CHIPID_TEGRA20) {
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if (ap20_is_odm_production_mode()) {
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printf("!! odm_production_mode is not supported !!\n");
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return MODE_UNDEFINED;
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} else
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if (ap20_is_production_mode())
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return MODE_PRODUCTION;
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else
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return MODE_UNDEFINED;
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}
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return MODE_UNDEFINED;
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}
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static void determine_crypto_options(int *is_encrypted, int *is_signed,
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int *use_zero_key)
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{
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switch (fuse_get_operation_mode()) {
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case MODE_PRODUCTION:
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*is_encrypted = 0;
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*is_signed = 1;
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*use_zero_key = 1;
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break;
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case MODE_UNDEFINED:
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default:
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*is_encrypted = 0;
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*is_signed = 0;
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*use_zero_key = 0;
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break;
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}
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}
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static int sign_wb_code(u32 start, u32 length, int use_zero_key)
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{
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int err;
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u8 *source; /* Pointer to source */
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u8 *hash;
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/* Calculate AES block parameters. */
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source = (u8 *)(start + offsetof(struct wb_header, random_aes_block));
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length -= offsetof(struct wb_header, random_aes_block);
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hash = (u8 *)(start + offsetof(struct wb_header, hash));
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err = sign_data_block(source, length, hash);
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return err;
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}
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int warmboot_prepare_code(u32 seg_address, u32 seg_length)
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{
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int err = 0;
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u32 length; /* length of the signed/encrypt code */
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struct wb_header *dst_header; /* Pointer to dest WB header */
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int is_encrypted; /* Segment is encrypted */
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int is_signed; /* Segment is signed */
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int use_zero_key; /* Use key of all zeros */
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/* Determine crypto options. */
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determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key);
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/* Get the actual code limits. */
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length = roundup(((u32)wb_end - (u32)wb_start), 16);
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/*
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* The region specified by seg_address must be in SDRAM and must be
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* nonzero in length.
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*/
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if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE ||
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seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) {
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err = -EFAULT;
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goto fail;
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}
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/* Things must be 16-byte aligned. */
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if ((seg_length & 0xF) || (seg_address & 0xF)) {
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err = -EINVAL;
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goto fail;
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}
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/* Will the code fit? (destination includes wb_header + wb code) */
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if (seg_length < (length + sizeof(struct wb_header))) {
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err = -EINVAL;
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goto fail;
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}
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dst_header = (struct wb_header *)seg_address;
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memset((char *)dst_header, 0, sizeof(struct wb_header));
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/* Populate the random_aes_block as requested. */
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{
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u32 *aes_block = (u32 *)&(dst_header->random_aes_block);
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u32 *end = (u32 *)(((u32)aes_block) +
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sizeof(dst_header->random_aes_block));
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do {
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*aes_block++ = 0;
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} while (aes_block < end);
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}
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/* Populate the header. */
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dst_header->length_insecure = length + sizeof(struct wb_header);
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dst_header->length_secure = length + sizeof(struct wb_header);
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dst_header->destination = NV_WB_RUN_ADDRESS;
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dst_header->entry_point = NV_WB_RUN_ADDRESS;
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dst_header->code_length = length;
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if (is_encrypted) {
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printf("!!!! Encryption is not supported !!!!\n");
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dst_header->length_insecure = 0;
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err = -EACCES;
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goto fail;
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} else
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/* copy the wb code directly following dst_header. */
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memcpy((char *)(dst_header+1), (char *)wb_start, length);
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if (is_signed)
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err = sign_wb_code(seg_address, dst_header->length_insecure,
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use_zero_key);
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fail:
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if (err)
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printf("Warning: warmboot code copy failed (error=%d)\n", err);
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return err;
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}
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