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https://github.com/brain-hackers/u-boot-brain
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![wdenk](/assets/img/avatar_default.png)
* Patch by Scott McNutt, 02 Jan 2004: Add support for the Nios Active Serial Memory Interface (ASMI) on Cyclone devices * Patch by Andrea Marson, 16 Dec 2003: Add support for the PPChameleon ME and HI modules * Patch by Yuli Barcohen, 22 Dec 2003: Add support for Motorola DUET ADS board (MPC87x/88x)
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/*
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* A collection of structures, addresses, and values associated with
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* the Motorola MPC8xxADS board. Copied from the FADS config.
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*
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
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*
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* Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
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*
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* Values common to all FADS family boards are in board/fads/fads.h
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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/* board type */
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#define CONFIG_MPC86xADS 1 /* new ADS */
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#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
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/* New MPC86xADS - pick one of these */
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#define CONFIG_MPC866T 1
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#undef CONFIG_MPC866P
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#undef CONFIG_MPC859T
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#undef CONFIG_MPC859DSL
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#undef CONFIG_MPC852T
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 38400
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# define CFG_8XX_FACT 5 /* Multiply by 5 */
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# define CFG_8XX_XIN 10000000 /* 10 MHz in */
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#define CONFIG_DRAM_50MHZ 1
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#define CONFIG_SDRAM_50MHZ 1
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 14-22
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*-----------------------------------------------------------------------
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* set the PLL, the low-power modes and the reset control
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*/
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#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
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#include "fads.h"
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#endif /* __CONFIG_H */
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