mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
245 lines
4.9 KiB
C
245 lines
4.9 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <serial.h>
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#include <linux/compiler.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#define US1_TDRE (1 << 7)
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#define US1_RDRF (1 << 5)
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#define US1_OR (1 << 3)
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#define UC2_TE (1 << 3)
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#define UC2_RE (1 << 2)
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#define CFIFO_TXFLUSH (1 << 7)
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#define CFIFO_RXFLUSH (1 << 6)
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#define SFIFO_RXOF (1 << 2)
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#define SFIFO_RXUF (1 << 0)
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#define STAT_LBKDIF (1 << 31)
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#define STAT_RXEDGIF (1 << 30)
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#define STAT_TDRE (1 << 23)
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#define STAT_RDRF (1 << 21)
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#define STAT_IDLE (1 << 20)
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#define STAT_OR (1 << 19)
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#define STAT_NF (1 << 18)
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#define STAT_FE (1 << 17)
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#define STAT_PF (1 << 16)
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#define STAT_MA1F (1 << 15)
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#define STAT_MA2F (1 << 14)
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#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
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STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
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#define CTRL_TE (1 << 19)
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#define CTRL_RE (1 << 18)
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#define FIFO_TXFE 0x80
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#define FIFO_RXFE 0x40
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#define WATER_TXWATER_OFF 1
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#define WATER_RXWATER_OFF 16
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DECLARE_GLOBAL_DATA_PTR;
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struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
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#ifndef CONFIG_LPUART_32B_REG
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static void lpuart_serial_setbrg(void)
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{
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u32 clk = mxc_get_clock(MXC_UART_CLK);
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u16 sbr;
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if (!gd->baudrate)
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gd->baudrate = CONFIG_BAUDRATE;
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sbr = (u16)(clk / (16 * gd->baudrate));
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/* place adjustment later - n/32 BRFA */
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__raw_writeb(sbr >> 8, &base->ubdh);
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__raw_writeb(sbr & 0xff, &base->ubdl);
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}
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static int lpuart_serial_getc(void)
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{
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while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
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WATCHDOG_RESET();
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barrier();
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return __raw_readb(&base->ud);
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}
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static void lpuart_serial_putc(const char c)
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{
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if (c == '\n')
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serial_putc('\r');
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while (!(__raw_readb(&base->us1) & US1_TDRE))
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WATCHDOG_RESET();
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__raw_writeb(c, &base->ud);
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}
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/*
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* Test whether a character is in the RX buffer
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*/
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static int lpuart_serial_tstc(void)
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{
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if (__raw_readb(&base->urcfifo) == 0)
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return 0;
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return 1;
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}
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/*
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*/
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static int lpuart_serial_init(void)
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{
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u8 ctrl;
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ctrl = __raw_readb(&base->uc2);
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ctrl &= ~UC2_RE;
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ctrl &= ~UC2_TE;
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__raw_writeb(ctrl, &base->uc2);
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__raw_writeb(0, &base->umodem);
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__raw_writeb(0, &base->uc1);
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/* Disable FIFO and flush buffer */
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__raw_writeb(0x0, &base->upfifo);
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__raw_writeb(0x0, &base->utwfifo);
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__raw_writeb(0x1, &base->urwfifo);
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__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
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/* provide data bits, parity, stop bit, etc */
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serial_setbrg();
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__raw_writeb(UC2_RE | UC2_TE, &base->uc2);
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return 0;
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}
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static struct serial_device lpuart_serial_drv = {
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.name = "lpuart_serial",
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.start = lpuart_serial_init,
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.stop = NULL,
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.setbrg = lpuart_serial_setbrg,
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.putc = lpuart_serial_putc,
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.puts = default_serial_puts,
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.getc = lpuart_serial_getc,
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.tstc = lpuart_serial_tstc,
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};
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#else
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static void lpuart32_serial_setbrg(void)
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{
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u32 clk = CONFIG_SYS_CLK_FREQ;
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u32 sbr;
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if (!gd->baudrate)
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gd->baudrate = CONFIG_BAUDRATE;
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sbr = (clk / (16 * gd->baudrate));
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/* place adjustment later - n/32 BRFA */
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out_be32(&base->baud, sbr);
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}
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static int lpuart32_serial_getc(void)
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{
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u32 stat;
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while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
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out_be32(&base->stat, STAT_FLAGS);
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WATCHDOG_RESET();
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}
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return in_be32(&base->data) & 0x3ff;
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}
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static void lpuart32_serial_putc(const char c)
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{
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if (c == '\n')
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serial_putc('\r');
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while (!(in_be32(&base->stat) & STAT_TDRE))
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WATCHDOG_RESET();
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out_be32(&base->data, c);
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}
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/*
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* Test whether a character is in the RX buffer
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*/
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static int lpuart32_serial_tstc(void)
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{
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if ((in_be32(&base->water) >> 24) == 0)
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return 0;
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return 1;
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}
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/*
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*/
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static int lpuart32_serial_init(void)
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{
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u8 ctrl;
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ctrl = in_be32(&base->ctrl);
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ctrl &= ~CTRL_RE;
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ctrl &= ~CTRL_TE;
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out_be32(&base->ctrl, ctrl);
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out_be32(&base->modir, 0);
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out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
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out_be32(&base->match, 0);
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/* provide data bits, parity, stop bit, etc */
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serial_setbrg();
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out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
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return 0;
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}
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static struct serial_device lpuart32_serial_drv = {
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.name = "lpuart32_serial",
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.start = lpuart32_serial_init,
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.stop = NULL,
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.setbrg = lpuart32_serial_setbrg,
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.putc = lpuart32_serial_putc,
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.puts = default_serial_puts,
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.getc = lpuart32_serial_getc,
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.tstc = lpuart32_serial_tstc,
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};
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#endif
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void lpuart_serial_initialize(void)
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{
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#ifdef CONFIG_LPUART_32B_REG
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serial_register(&lpuart32_serial_drv);
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#else
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serial_register(&lpuart_serial_drv);
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#endif
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}
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__weak struct serial_device *default_serial_console(void)
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{
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#ifdef CONFIG_LPUART_32B_REG
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return &lpuart32_serial_drv;
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#else
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return &lpuart_serial_drv;
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#endif
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}
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