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https://github.com/brain-hackers/u-boot-brain
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![Adam Ford](/assets/img/avatar_default.png)
arch/arm/Makefile references armv5 for backwards compatibility with older compilers. This patch removes those references to armv5, since by now newer compilers are required which should have armv7 support enabled. The Makefile also also has a list of options for mtune, but the entry for CONFIG_CPU_V7A is empty, so this patch tunes the CPU_V7A architecture to generic-armv7-a. The following size changed apply to omap3_logic using GCC. Stock text data bss dec hex filename 50910 429 67580 118919 1d087 spl/u-boot-spl 540713 22700 327072 890485 d9675 u-boot Without Armv5 text data bss dec hex filename 50916 429 67580 118925 1d08d spl/u-boot-spl 540719 22700 327064 890483 d9673 u-boot mtune=generic-armv7-a text data bss dec hex filename 50932 429 67580 118941 1d09d spl/u-boot-spl 540519 22700 327080 890299 d95bb u-boot Signed-off-by: Adam Ford <aford173@gmail.com>
210 lines
4.4 KiB
Plaintext
210 lines
4.4 KiB
Plaintext
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Summary
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=======
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This README is about U-Boot support for TI's ARM Cortex-A8 based OMAP3 [1]
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family of SoCs. TI's OMAP3 SoC family contains an ARM Cortex-A8. Additionally,
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some family members contain a TMS320C64x+ DSP and/or an Imagination SGX 2D/3D
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graphics processor and various other standard peripherals.
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Currently the following boards are supported:
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* OMAP3530 BeagleBoard [2]
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* Gumstix Overo [3]
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* TI EVM [4]
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* OpenPandora Ltd. Pandora [5]
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* TI/Logic PD Zoom MDK [6]
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* TI/Logic PD Zoom 2 [7]
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* CompuLab Ltd. CM-T35 [8]
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Build
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=====
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* BeagleBoard:
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make omap3_beagle_config
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make
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* Gumstix Overo:
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make omap3_overo_config
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make
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* TI EVM:
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make omap3_evm_config
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make
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* Pandora:
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make omap3_pandora_config
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make
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* Zoom MDK:
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make omap3_zoom1_config
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make
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* Zoom 2:
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make omap3_zoom2_config
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make
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* CM-T35:
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make cm_t35_config
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make
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Custom commands
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===============
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To make U-Boot for OMAP3 support NAND device SW or HW ECC calculation, U-Boot
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for OMAP3 supports custom user command
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nandecc hw/sw
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To be compatible with NAND drivers using SW ECC (e.g. kernel code)
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nandecc sw
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enables SW ECC calculation. HW ECC enabled with
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nandecc hw
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is typically used to write 2nd stage bootloader (known as 'x-loader') which is
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executed by OMAP3's boot rom and therefore has to be written with HW ECC.
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For all other commands see
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help
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Interfaces
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==========
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gpio
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----
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To set a bit :
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if (!gpio_request(N, "")) {
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gpio_direction_output(N, 0);
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gpio_set_value(N, 1);
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}
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To clear a bit :
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if (!gpio_request(N, "")) {
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gpio_direction_output(N, 0);
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gpio_set_value(N, 0);
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}
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To read a bit :
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if (!gpio_request(N, "")) {
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gpio_direction_input(N);
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val = gpio_get_value(N);
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gpio_free(N);
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}
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if (val)
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printf("GPIO N is set\n");
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else
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printf("GPIO N is clear\n");
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dma
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---
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void omap3_dma_init(void)
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Init the DMA module
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int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
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Read config of the channel
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int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
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Write config to the channel
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int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
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uint32_t sze)
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Config source, destination and size of a transfer
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int omap3_dma_wait_for_transfer(uint32_t chan)
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Wait for a transfer to end - this hast to be called before a channel
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or the data the channel transferd are used.
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int omap3_dma_get_revision(uint32_t *minor, uint32_t *major)
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Read silicon Revision of the DMA module
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NAND
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====
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There are some OMAP3 devices out there with NAND attached. Due to the fact that
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OMAP3 ROM code can only handle 1-bit hamming ECC for accessing first page
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(place where SPL lives) we require this setup for u-boot at least when reading
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the second progam within SPL. A lot of newer NAND chips however require more
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than 1-bit ECC for the pages, some can live with 1-bit for the first page. To
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handle this we can switch to another ECC algorithm after reading the payload
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within SPL.
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BCH8
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----
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To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on
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OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH
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and set CONFIG_NAND_OMAP_ECCSCHEME=5 (refer README.nand) for selecting BCH8_SW.
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The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8
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implementation for OMAP3 works for you so the u-boot version should also.
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When you require the SPL to read with BCH8 there are two more configs to
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change:
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* CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in
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GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in
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arch/arm/include/asm/arch-omap3/omap_gpmc.h)
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* CONFIG_SYS_NAND_ECCSIZE must be 512
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* CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
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Acknowledgements
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================
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OMAP3 U-Boot is based on U-Boot tar ball [9] for BeagleBoard and EVM done by
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several TI employees.
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Links
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=====
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[1] OMAP3:
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http://www.ti.com/omap3 (high volume) and
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http://www.ti.com/omap35x (broad market)
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[2] OMAP3530 BeagleBoard:
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http://beagleboard.org/
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[3] Gumstix Overo:
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http://www.gumstix.net/Overo/
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[4] TI EVM:
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http://focus.ti.com/docs/toolsw/folders/print/tmdxevm3503.html
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[5] OpenPandora Ltd. Pandora:
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http://openpandora.org/
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[6] TI/Logic PD Zoom MDK:
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http://www.logicpd.com/products/devkit/ti/zoom_mobile_development_kit
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[7] TI/Logic PD Zoom 2
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http://www.logicpd.com/sites/default/files/1012659A_Zoom_OMAP34x-II_MDP_Brief.pdf
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[8] CompuLab Ltd. CM-T35:
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http://www.compulab.co.il/t3530/html/t3530-cm-datasheet.htm
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[9] TI OMAP3 U-Boot:
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http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz
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