mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-29 22:33:44 +09:00
3d9569b232
On PPC44x platforms, the startup message generated in "cpu.c" only comprised the ppc type and revision but not additional informations like speed etc. Those speed infos where printed in the board specific code. This new implementation now prints all CPU infos in the common cpu specific code. No board specific code is needed anymore and therefore removed from all current 44x implementations. Patch by Stefan Roese, 27 Nov 2005
407 lines
16 KiB
C
407 lines
16 KiB
C
/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* bamboo.h - configuration for BAMBOO board
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
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#define CONFIG_440EP 1 /* Specific PPC440EP support */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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/*
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* Please note that, if NAND support is enabled, the 2nd ethernet port
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* can't be used because of pin multiplexing. So, if you want to use the
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* 2nd ethernet port you have to "undef" the following define.
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*/
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#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
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#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
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#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
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#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
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#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
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/*Don't change either of these*/
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#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
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#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
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/*Don't change either of these*/
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#define CFG_USB_DEVICE 0x50000000
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#define CFG_NVRAM_BASE_ADDR 0x80000000
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#define CFG_BOOT_BASE_ADDR 0xf0000000
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#define CFG_NAND_ADDR 0x90000000
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#define CFG_NAND2_ADDR 0x94000000
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in SDRAM)
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*----------------------------------------------------------------------*/
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#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI 1
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/* define this if you want console on UART1 */
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#undef CONFIG_UART1_CONSOLE
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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* NVRAM/RTC
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*
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* NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
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* The DS1558 code assumes this condition
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*
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*----------------------------------------------------------------------*/
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#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
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#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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/*
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* Define here the location of the environment variables (FLASH or EEPROM).
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* Note: DENX encourages to use redundant environment in FLASH.
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*/
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#if 1
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#endif
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
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#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_ADDR0 0x555
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#define CFG_FLASH_ADDR1 0x2aa
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#define CFG_FLASH_WORD_SIZE unsigned char
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#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
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#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif /* CFG_ENV_IS_IN_FLASH */
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/*-----------------------------------------------------------------------
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* NAND-FLASH related
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*----------------------------------------------------------------------*/
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#define NAND_CMD_REG (0x00) /* NandFlash Command Register */
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#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */
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#define NAND_DATA_REG (0x08) /* NandFlash Data Register */
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#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */
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#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */
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#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */
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#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */
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#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */
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#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */
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#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */
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#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */
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#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */
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#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */
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#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */
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#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */
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#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */
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#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */
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#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
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#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
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/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
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#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */
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#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */
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#define NAND0_CMD_READ2 0x50
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#define NAND0_CMD_READ_ID 0x90
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#define NAND0_CMD_READ_STATUS 0x70
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#define NAND0_CMD_RESET 0xFF
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#define NAND0_CMD_PAGE_PROG 0x80
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#define NAND0_CMD_PAGE_PROG_TRUE 0x10
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#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
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#define NAND0_CMD_BLOCK_ERASE 0x60
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#define NAND0_CMD_BLOCK_ERASE_END 0xD0
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
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#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
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#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
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#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
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#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
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/* not needed with 440EP NAND controller */
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#define NAND_CTL_CLRALE(nandptr)
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#define NAND_CTL_SETALE(nandptr)
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#define NAND_CTL_CLRCLE(nandptr)
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#define NAND_CTL_SETCLE(nandptr)
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#define NAND_DISABLE_CE(nand)
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#define NAND_ENABLE_CE(nand)
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------------- */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#undef CONFIG_DDR_ECC /* don't use ECC */
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#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
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#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_MULTI_EEPROMS
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#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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#ifdef CFG_ENV_IS_IN_EEPROM
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#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
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#define CFG_ENV_OFFSET 0x0
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#endif /* CFG_ENV_IS_IN_EEPROM */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"hostname=bamboo\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"bootfile=/tftpboot/bamboo/uImage\0" \
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"kernel_addr=fff00000\0" \
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"ramdisk_addr=fff10000\0" \
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"load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \
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"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
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"cp.b 100000 fff80000 80000;" \
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"setenv filesize;saveenv\0" \
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"upd=run load;run update\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
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#define CONFIG_PHY1_ADDR 1
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#ifndef CONFIG_BAMBOO_NAND
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#endif /* CONFIG_BAMBOO_NAND */
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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#define CONFIG_NET_MULTI 1 /* required for netconsole */
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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#ifdef CONFIG_440EP
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/* USB */
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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/*Comment this out to enable USB 1.1 device*/
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#define USB_2_0_DEVICE
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#endif /*CONFIG_440EP*/
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#ifdef CONFIG_BAMBOO_NAND
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#define _CFG_CMD_NAND CFG_CMD_NAND
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#else
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#define _CFG_CMD_NAND 0
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#endif /* CONFIG_BAMBOO_NAND */
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_EEPROM | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_DIAG | \
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CFG_CMD_ELF | \
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CFG_CMD_I2C | \
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CFG_CMD_IRQ | \
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CFG_CMD_MII | \
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CFG_CMD_NET | \
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CFG_CMD_NFS | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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CFG_CMD_USB | \
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CFG_CMD_FAT | \
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CFG_CMD_EXT2 | \
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_CFG_CMD_NAND | \
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CFG_CMD_SNTP )
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#define CONFIG_SUPPORT_VFAT
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_LYNXKDI 1 /* support kdi files */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
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/* Board-specific PCI */
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#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
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#define CFG_PCI_TARGET_INIT
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#define CFG_PCI_MASTER_INIT
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#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
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#define CFG_CACHELINE_SIZE 32 /* ... */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#endif /* __CONFIG_H */
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