mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
597 lines
17 KiB
C
597 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Novena SPL
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*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/crm_regs.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <spl.h>
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#include <asm/arch/mx6-ddr.h>
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#include "novena.h"
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#define UART_PAD_CTRL \
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(PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL \
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(PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL \
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(PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define ENET_PHY_CFG_PAD_CTRL \
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(PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_HYS)
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#define RGMII_PAD_CTRL \
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(PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define SPI_PAD_CTRL \
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(PAD_CTL_HYS | \
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PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL \
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(PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE)
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#define BUTTON_PAD_CTRL \
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(PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/*
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* Audio
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*/
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static iomux_v3_cfg_t audio_pads[] = {
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/* AUD_PWRON */
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MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void novena_spl_setup_iomux_audio(void)
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{
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imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads));
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gpio_direction_output(NOVENA_AUDIO_PWRON, 1);
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}
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/*
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* ENET
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*/
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static iomux_v3_cfg_t enet_pads1[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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/* pin 35, PHY_AD2 */
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MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
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/* pin 32, MODE0 */
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MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
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/* pin 31, MODE1 */
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MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
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/* pin 28, MODE2 */
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MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
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/* pin 27, MODE3 */
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MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
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/* pin 33, CLK125_EN */
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MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
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/* pin 42 PHY nRST */
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MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t enet_pads2[] = {
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
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};
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static void novena_spl_setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
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/* Assert Ethernet PHY nRST */
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gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
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/*
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* Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
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* de-assertion. The intention is to use weak signal drivers (pull-ups)
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* to prevent the conflict between PHY pins becoming outputs after
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* reset and imx6 still driving the pins. The issue is described in PHY
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* datasheet, p.14
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*/
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gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
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gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
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gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
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gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
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gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
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gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
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/* Following reset timing (p.53, fig.8 from the PHY datasheet) */
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mdelay(10);
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/* De-assert Ethernet PHY nRST */
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gpio_set_value(IMX_GPIO_NR(3, 23), 1);
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/* PHY is now configured, connect FEC to the pads */
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imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
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/*
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* PHY datasheet recommends on p.53 to wait at least 100us after reset
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* before using MII, so we enforce the delay here
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*/
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udelay(100);
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}
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/*
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* FPGA
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*/
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static iomux_v3_cfg_t fpga_pads[] = {
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/* FPGA_RESET_N */
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MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void novena_spl_setup_iomux_fpga(void)
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{
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imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads));
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gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0);
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}
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/*
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* GPIO Button
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*/
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static iomux_v3_cfg_t button_pads[] = {
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/* Debug */
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MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
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};
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static void novena_spl_setup_iomux_buttons(void)
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{
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imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads));
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}
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/*
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* I2C
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*/
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/*
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* I2C1:
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* 0x1d ... MMA7455L
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* 0x30 ... SO-DIMM temp sensor
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* 0x44 ... STMPE610
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* 0x50 ... SO-DIMM ID
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*/
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struct i2c_pads_info i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
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.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
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.gp = IMX_GPIO_NR(3, 21)
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},
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.sda = {
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.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
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.gp = IMX_GPIO_NR(3, 28)
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}
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};
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/*
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* I2C2:
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* 0x08 ... PMIC
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* 0x3a ... HDMI DCC
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* 0x50 ... HDMI DCC
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*/
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
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.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
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.gp = IMX_GPIO_NR(2, 30)
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},
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.sda = {
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.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
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.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
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.gp = IMX_GPIO_NR(3, 16)
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}
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};
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/*
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* I2C3:
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* 0x11 ... ES8283
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* 0x50 ... LCD EDID
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* 0x56 ... EEPROM
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*/
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static struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
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.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
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.gp = IMX_GPIO_NR(3, 17)
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},
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.sda = {
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.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
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.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
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.gp = IMX_GPIO_NR(3, 18)
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}
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};
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static void novena_spl_setup_iomux_i2c(void)
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{
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
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}
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/*
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* PCI express
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*/
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#ifdef CONFIG_CMD_PCI
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static iomux_v3_cfg_t pcie_pads[] = {
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/* "Reset" pin */
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MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* "Power on" pin */
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MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* "Wake up" pin (input) */
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MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* "Disable endpoint" (rfkill) pin */
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MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void novena_spl_setup_iomux_pcie(void)
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{
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imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
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/* Ensure PCIe is powered down */
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gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0);
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/* Put the card into reset */
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gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0);
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/* Input signal to wake system from mPCIe card */
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gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO);
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/* Drive RFKILL high, to ensure the radio is turned on */
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gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1);
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}
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#else
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static inline void novena_spl_setup_iomux_pcie(void) {}
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#endif
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/*
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* SDHC
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*/
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static iomux_v3_cfg_t usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
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MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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static iomux_v3_cfg_t usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static void novena_spl_setup_iomux_sdhc(void)
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{
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imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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/* Big SD write-protect and card-detect */
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gpio_direction_input(IMX_GPIO_NR(1, 2));
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gpio_direction_input(IMX_GPIO_NR(1, 4));
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}
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/*
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* SPI
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*/
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#ifdef CONFIG_MXC_SPI
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static iomux_v3_cfg_t ecspi3_pads[] = {
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/* SS1 */
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MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL),
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};
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static void novena_spl_setup_iomux_spi(void)
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{
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imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
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/* De-assert the nCS */
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gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1);
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gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1);
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gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1);
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}
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#else
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static void novena_spl_setup_iomux_spi(void) {}
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#endif
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/*
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* UART
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*/
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static iomux_v3_cfg_t const uart2_pads[] = {
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MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart3_pads[] = {
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MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart4_pads[] = {
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MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void novena_spl_setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
|
|
imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
|
|
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
|
|
}
|
|
|
|
/*
|
|
* Video
|
|
*/
|
|
#ifdef CONFIG_VIDEO
|
|
static iomux_v3_cfg_t hdmi_pads[] = {
|
|
/* "Ghost HPD" pin */
|
|
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
|
|
/* LCD_PWR_CTL */
|
|
MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
/* LCD_BL_ON */
|
|
MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
/* GPIO_PWM1 */
|
|
MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
static void novena_spl_setup_iomux_video(void)
|
|
{
|
|
imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
|
|
gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
|
|
}
|
|
#else
|
|
static inline void novena_spl_setup_iomux_video(void) {}
|
|
#endif
|
|
|
|
/*
|
|
* SPL boots from uSDHC card
|
|
*/
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
static struct fsl_esdhc_cfg usdhc_cfg = {
|
|
USDHC3_BASE_ADDR, 0, 4
|
|
};
|
|
|
|
int board_mmc_getcd(struct mmc *mmc)
|
|
{
|
|
/* There is no CD for a microSD card, assume always present. */
|
|
return 1;
|
|
}
|
|
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
return fsl_esdhc_initialize(bis, &usdhc_cfg);
|
|
}
|
|
#endif
|
|
|
|
/* Configure MX6Q/DUAL mmdc DDR io registers */
|
|
static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
|
|
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
|
|
.dram_sdclk_0 = 0x00020038,
|
|
.dram_sdclk_1 = 0x00020038,
|
|
.dram_cas = 0x00000038,
|
|
.dram_ras = 0x00000038,
|
|
.dram_reset = 0x00000038,
|
|
/* SDCKE[0:1]: 100k pull-up */
|
|
.dram_sdcke0 = 0x00000038,
|
|
.dram_sdcke1 = 0x00000038,
|
|
/* SDBA2: pull-up disabled */
|
|
.dram_sdba2 = 0x00000000,
|
|
/* SDODT[0:1]: 100k pull-up, 40 ohm */
|
|
.dram_sdodt0 = 0x00000038,
|
|
.dram_sdodt1 = 0x00000038,
|
|
/* SDQS[0:7]: Differential input, 40 ohm */
|
|
.dram_sdqs0 = 0x00000038,
|
|
.dram_sdqs1 = 0x00000038,
|
|
.dram_sdqs2 = 0x00000038,
|
|
.dram_sdqs3 = 0x00000038,
|
|
.dram_sdqs4 = 0x00000038,
|
|
.dram_sdqs5 = 0x00000038,
|
|
.dram_sdqs6 = 0x00000038,
|
|
.dram_sdqs7 = 0x00000038,
|
|
|
|
/* DQM[0:7]: Differential input, 40 ohm */
|
|
.dram_dqm0 = 0x00000038,
|
|
.dram_dqm1 = 0x00000038,
|
|
.dram_dqm2 = 0x00000038,
|
|
.dram_dqm3 = 0x00000038,
|
|
.dram_dqm4 = 0x00000038,
|
|
.dram_dqm5 = 0x00000038,
|
|
.dram_dqm6 = 0x00000038,
|
|
.dram_dqm7 = 0x00000038,
|
|
};
|
|
|
|
/* Configure MX6Q/DUAL mmdc GRP io registers */
|
|
static struct mx6dq_iomux_grp_regs novena_grp_ioregs = {
|
|
/* DDR3 */
|
|
.grp_ddr_type = 0x000c0000,
|
|
.grp_ddrmode_ctl = 0x00020000,
|
|
/* Disable DDR pullups */
|
|
.grp_ddrpke = 0x00000000,
|
|
/* ADDR[00:16], SDBA[0:1]: 40 ohm */
|
|
.grp_addds = 0x00000038,
|
|
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
|
|
.grp_ctlds = 0x00000038,
|
|
/* DATA[00:63]: Differential input, 40 ohm */
|
|
.grp_ddrmode = 0x00020000,
|
|
.grp_b0ds = 0x00000038,
|
|
.grp_b1ds = 0x00000038,
|
|
.grp_b2ds = 0x00000038,
|
|
.grp_b3ds = 0x00000038,
|
|
.grp_b4ds = 0x00000038,
|
|
.grp_b5ds = 0x00000038,
|
|
.grp_b6ds = 0x00000038,
|
|
.grp_b7ds = 0x00000038,
|
|
};
|
|
|
|
static struct mx6_mmdc_calibration novena_mmdc_calib = {
|
|
/* write leveling calibration determine */
|
|
.p0_mpwldectrl0 = 0x00420048,
|
|
.p0_mpwldectrl1 = 0x006f0059,
|
|
.p1_mpwldectrl0 = 0x005a0104,
|
|
.p1_mpwldectrl1 = 0x01070113,
|
|
/* Read DQS Gating calibration */
|
|
.p0_mpdgctrl0 = 0x437c040b,
|
|
.p0_mpdgctrl1 = 0x0413040e,
|
|
.p1_mpdgctrl0 = 0x444f0446,
|
|
.p1_mpdgctrl1 = 0x044d0422,
|
|
/* Read Calibration: DQS delay relative to DQ read access */
|
|
.p0_mprddlctl = 0x4c424249,
|
|
.p1_mprddlctl = 0x4e48414f,
|
|
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
|
.p0_mpwrdlctl = 0x42414641,
|
|
.p1_mpwrdlctl = 0x46374b43,
|
|
};
|
|
|
|
static struct mx6_ddr_sysinfo novena_ddr_info = {
|
|
/* Width of data bus: 0=16, 1=32, 2=64 */
|
|
.dsize = 2,
|
|
/* Config for full 4GB range so that get_mem_size() works */
|
|
.cs_density = 32, /* 32Gb per CS */
|
|
/* Single chip select */
|
|
.ncs = 1,
|
|
.cs1_mirror = 0,
|
|
.rtt_wr = 0, /* RTT_Wr = RZQ/4 */
|
|
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
|
|
.walat = 0, /* Write additional latency */
|
|
.ralat = 5, /* Read additional latency */
|
|
.mif3_mode = 3, /* Command prediction working mode */
|
|
.bi_on = 1, /* Bank interleaving enabled */
|
|
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
|
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
|
.refsel = 1, /* Refresh cycles at 32KHz */
|
|
.refr = 7, /* 8 refresh commands per refresh cycle */
|
|
};
|
|
|
|
static struct mx6_ddr3_cfg elpida_4gib_1600 = {
|
|
.mem_speed = 1600,
|
|
.density = 4,
|
|
.width = 64,
|
|
.banks = 8,
|
|
.rowaddr = 16,
|
|
.coladdr = 10,
|
|
.pagesz = 2,
|
|
.trcd = 1375,
|
|
.trcmin = 4875,
|
|
.trasmin = 3500,
|
|
};
|
|
|
|
static void ccgr_init(void)
|
|
{
|
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
writel(0x00C03F3F, &ccm->CCGR0);
|
|
writel(0x0030FC03, &ccm->CCGR1);
|
|
writel(0x0FFFC000, &ccm->CCGR2);
|
|
writel(0x3FF00000, &ccm->CCGR3);
|
|
writel(0xFFFFF300, &ccm->CCGR4);
|
|
writel(0x0F0000C3, &ccm->CCGR5);
|
|
writel(0x000003FF, &ccm->CCGR6);
|
|
}
|
|
|
|
/*
|
|
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
|
|
* - we have a stack and a place to store GD, both in SRAM
|
|
* - no variable global data is available
|
|
*/
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
/* setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
ccgr_init();
|
|
gpr_init();
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
#ifdef CONFIG_BOARD_POSTCLK_INIT
|
|
board_postclk_init();
|
|
#endif
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
get_clocks();
|
|
#endif
|
|
|
|
/* Setup IOMUX and configure basics. */
|
|
novena_spl_setup_iomux_audio();
|
|
novena_spl_setup_iomux_buttons();
|
|
novena_spl_setup_iomux_enet();
|
|
novena_spl_setup_iomux_fpga();
|
|
novena_spl_setup_iomux_i2c();
|
|
novena_spl_setup_iomux_pcie();
|
|
novena_spl_setup_iomux_sdhc();
|
|
novena_spl_setup_iomux_spi();
|
|
novena_spl_setup_iomux_uart();
|
|
novena_spl_setup_iomux_video();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
/* Start the DDR DRAM */
|
|
mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
|
|
mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
|
|
|
|
/* Perform DDR DRAM calibration */
|
|
udelay(100);
|
|
mmdc_do_write_level_calibration(&novena_ddr_info);
|
|
mmdc_do_dqs_calibration(&novena_ddr_info);
|
|
}
|