Stephen Warren 790f7719e2 ARM: tegra: pinmux: account for different drivegroup base registers ... Tegra210 starts its drive group registers at a different offset from the APB MISC register block that other SoCs. Update the code to handle this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>		2015-03-04 10:09:01 -07:00
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clock-tables.h	Tegra30: clocks: Fix clock tables for I2C and other periphs	2013-01-16 13:40:08 -07:00
clock.h	ARM: tegra: Implement tegra_plle_enable()	2014-12-18 13:19:20 -07:00
flow.h	Tegra30: Add arch-tegra30 include files	2013-01-16 13:40:07 -07:00
funcmux.h	Tegra30: Add arch-tegra30 include files	2013-01-16 13:40:07 -07:00
gp_padctrl.h	Tegra30: Cardhu: Add pad config tables/code based on pinmux code	2013-03-14 11:06:43 -07:00
gpio.h	Tegra30: Add arch-tegra30 include files	2013-01-16 13:40:07 -07:00
hardware.h	Tegra30: Add arch-tegra30 include files	2013-01-16 13:40:07 -07:00
mc.h	ARM: tegra: Use mem size from MC in combination with get_ram_size()	2014-10-22 09:30:55 -07:00
pinmux.h	ARM: tegra: pinmux: account for different drivegroup base registers	2015-03-04 10:09:01 -07:00
pmu.h	Tegra30: Add arch-tegra30 include files	2013-01-16 13:40:07 -07:00
powergate.h	ARM: tegra: Implement powergate support	2014-12-18 13:19:20 -07:00
tegra.h	ARM: tegra: Use mem size from MC in combination with get_ram_size()	2014-10-22 09:30:55 -07:00