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https://github.com/brain-hackers/u-boot-brain
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a186e8aa67
This affects RK3036, RK322X and RK3288 - the defconfig changes done by moveconfig.py for the veyrons were left out on purpose because they dont have an OTG port, and will get their config updated in the next commit. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2015 Rockchip Electronics Co., Ltd
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*/
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#ifndef __CONFIG_RK3036_COMMON_H
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#define __CONFIG_RK3036_COMMON_H
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#include <asm/arch-rockchip/hardware.h>
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#include "rockchip-common.h"
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
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#define COUNTER_FREQUENCY 24000000
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#define CONFIG_SYS_ARCH_TIMER
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#define CONFIG_SYS_HZ_CLOCK 24000000
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#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
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#define CONFIG_SYS_LOAD_ADDR 0x60800800
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#define CONFIG_SPL_STACK 0x10081fff
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#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10)
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#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
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#define CONFIG_SYS_SDRAM_BASE 0x60000000
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#define SDRAM_BANK_SIZE (512UL << 20UL)
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#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
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#ifndef CONFIG_SPL_BUILD
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x60000000\0" \
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"pxefile_addr_r=0x60100000\0" \
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"fdt_addr_r=0x61f00000\0" \
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"kernel_addr_r=0x62000000\0" \
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"ramdisk_addr_r=0x64000000\0"
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#include <config_distro_bootcmd.h>
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/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
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* so limit the fdt reallocation to that */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"fdt_high=0x7fffffff\0" \
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"partitions=" PARTS_DEFAULT \
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ENV_MEM_LAYOUT_SETTINGS \
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BOOTENV
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#endif
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#endif
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