mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
446 lines
11 KiB
C
446 lines
11 KiB
C
/*
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* (C) Copyright 2001
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* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* evb64260.c - main board support/init for the Galileo Eval board.
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*/
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#include <common.h>
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#include <74xx_7xx.h>
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#include <galileo/memory.h>
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#include <galileo/pci.h>
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#include <galileo/gt64260R.h>
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#include <net.h>
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#include <asm/io.h>
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#include "eth.h"
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#include "mpsc.h"
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#include "i2c.h"
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#include "64260.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_ZUMA_V2
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extern void zuma_mbox_init(void);
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#endif
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#undef DEBUG
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#define MAP_PCI
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#ifdef DEBUG
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#define DP(x) x
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#else
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#define DP(x)
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#endif
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/* ------------------------------------------------------------------------- */
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/* this is the current GT register space location */
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/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
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/* Unfortunately, we cant change it while we are in flash, so we initialize it
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* to the "final" value. This means that any debug_led calls before
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* board_early_init_f wont work right (like in cpu_init_f).
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* See also my_remap_gt_regs below. (NTL)
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*/
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unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
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/* ------------------------------------------------------------------------- */
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/*
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* This is a version of the GT register space remapping function that
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* doesn't touch globals (meaning, it's ok to run from flash.)
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*
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* Unfortunately, this has the side effect that a writable
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* INTERNAL_REG_BASE_ADDR is impossible. Oh well.
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*/
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void
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my_remap_gt_regs(u32 cur_loc, u32 new_loc)
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{
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u32 temp;
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/* check and see if it's already moved */
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temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
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if ((temp & 0xffff) == new_loc >> 20)
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return;
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temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
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0xffff0000) | (new_loc >> 20);
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out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
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while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
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}
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static void
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gt_pci_config(void)
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{
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/* move PCI stuff out of the way - NTL */
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/* map PCI Host 0 */
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pciMapSpace(PCI_HOST0, PCI_REGION0, CFG_PCI0_0_MEM_SPACE,
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CFG_PCI0_0_MEM_SPACE, CFG_PCI0_MEM_SIZE);
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pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0);
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pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0);
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pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0);
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pciMapSpace(PCI_HOST0, PCI_IO, CFG_PCI0_IO_SPACE_PCI,
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CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE);
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/* map PCI Host 1 */
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pciMapSpace(PCI_HOST1, PCI_REGION0, CFG_PCI1_0_MEM_SPACE,
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CFG_PCI1_0_MEM_SPACE, CFG_PCI1_MEM_SIZE);
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pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0);
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pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0);
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pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0);
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pciMapSpace(PCI_HOST1, PCI_IO, CFG_PCI1_IO_SPACE_PCI,
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CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE);
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/* PCI interface settings */
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GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff);
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GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff);
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GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
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GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
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}
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/* Setup CPU interface paramaters */
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static void
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gt_cpu_config(void)
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{
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cpu_t cpu = get_cpu_type();
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ulong tmp;
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/* cpu configuration register */
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tmp = GTREGREAD(CPU_CONFIGURATION);
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/* set the AACK delay bit
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* see Res#14 */
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tmp |= CPU_CONF_AACK_DELAY;
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tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */
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/* Galileo claims this is necessary for all busses >= 100 MHz */
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tmp |= CPU_CONF_FAST_CLK;
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if (cpu == CPU_750CX) {
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tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */
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tmp &= ~CPU_CONF_AP_VALID;
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} else {
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tmp |= CPU_CONF_DP_VALID;
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tmp |= CPU_CONF_AP_VALID;
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}
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/* this only works with the MPX bus */
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tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */
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tmp |= CPU_CONF_PIPELINE;
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tmp |= CPU_CONF_TA_DELAY;
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GT_REG_WRITE(CPU_CONFIGURATION, tmp);
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/* CPU master control register */
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tmp = GTREGREAD(CPU_MASTER_CONTROL);
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tmp |= CPU_MAST_CTL_ARB_EN;
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if ((cpu == CPU_7400) ||
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(cpu == CPU_7410) ||
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(cpu == CPU_7450)) {
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tmp |= CPU_MAST_CTL_CLEAN_BLK;
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tmp |= CPU_MAST_CTL_FLUSH_BLK;
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} else {
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/* cleanblock must be cleared for CPUs
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* that do not support this command
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* see Res#1 */
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tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
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tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
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}
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GT_REG_WRITE(CPU_MASTER_CONTROL, tmp);
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}
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/*
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* board_early_init_f.
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*
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* set up gal. device mappings, etc.
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*/
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int board_early_init_f (void)
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{
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uchar sram_boot = 0;
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/*
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* set up the GT the way the kernel wants it
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* the call to move the GT register space will obviously
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* fail if it has already been done, but we're going to assume
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* that if it's not at the power-on location, it's where we put
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* it last time. (huber)
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*/
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my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS);
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gt_pci_config();
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/* mask all external interrupt sources */
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GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
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GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
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GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
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GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
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GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
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GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
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GT_REG_WRITE(CPU_INT_0_MASK, 0);
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GT_REG_WRITE(CPU_INT_1_MASK, 0);
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GT_REG_WRITE(CPU_INT_2_MASK, 0);
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GT_REG_WRITE(CPU_INT_3_MASK, 0);
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/* now, onto the configuration */
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GT_REG_WRITE(SDRAM_CONFIGURATION, CFG_SDRAM_CONFIG);
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/* ----- DEVICE BUS SETTINGS ------ */
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/*
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* EVB
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* 0 - SRAM
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* 1 - RTC
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* 2 - UART
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* 3 - Flash
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* boot - BootCS
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*
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* Zuma
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* 0 - Flash
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* boot - BootCS
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*/
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/*
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* the dual 7450 module requires burst access to the boot
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* device, so the serial rom copies the boot device to the
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* on-board sram on the eval board, and updates the correct
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* registers to boot from the sram. (device0)
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*/
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#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
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/* Zuma has no SRAM */
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sram_boot = 0;
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#else
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if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CFG_MONITOR_BASE)
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sram_boot = 1;
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#endif
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if (!sram_boot)
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memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
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memoryMapDeviceSpace(DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
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memoryMapDeviceSpace(DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
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memoryMapDeviceSpace(DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
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/* configure device timing */
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#ifdef CFG_DEV0_PAR
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if (!sram_boot)
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GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
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#endif
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#ifdef CFG_DEV1_PAR
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GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
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#endif
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#ifdef CFG_DEV2_PAR
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GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
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#endif
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#ifdef CONFIG_EVB64260
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#ifdef CFG_32BIT_BOOT_PAR
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/* detect if we are booting from the 32 bit flash */
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if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
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/* 32 bit boot flash */
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GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
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GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_32BIT_BOOT_PAR);
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} else {
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/* 8 bit boot flash */
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GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
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GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
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}
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#else
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/* 8 bit boot flash only */
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GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
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#endif
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#else /* CONFIG_EVB64260 not defined */
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/* We are booting from 16-bit flash.
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*/
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GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_16BIT_BOOT_PAR);
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#endif
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gt_cpu_config();
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/* MPP setup */
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GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0);
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GT_REG_WRITE(MPP_CONTROL1, CFG_MPP_CONTROL_1);
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GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2);
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GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3);
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GT_REG_WRITE(GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
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GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CFG_SERIAL_PORT_MUX);
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return 0;
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}
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/* various things to do after relocation */
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int misc_init_r (void)
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{
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icache_enable();
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#ifdef CFG_L2
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l2cache_enable();
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#endif
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#ifdef CONFIG_MPSC
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mpsc_init2();
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#endif
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#ifdef CONFIG_ZUMA_V2
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zuma_mbox_init();
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#endif
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return (0);
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}
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void
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after_reloc(ulong dest_addr)
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{
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/* check to see if we booted from the sram. If so, move things
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* back to the way they should be. (we're running from main
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* memory at this point now */
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if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) {
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memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
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memoryMapDeviceSpace(BOOT_DEVICE, CFG_FLASH_BASE, _1M);
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}
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/* now, jump to the main U-Boot board init code */
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board_init_r ((gd_t *)gd, dest_addr);
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/* NOTREACHED */
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int
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checkboard (void)
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{
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puts ("Board: " CFG_BOARD_NAME "\n");
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return (0);
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}
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/* utility functions */
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void
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debug_led(int led, int mode)
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{
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#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4)
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volatile int *addr = NULL;
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int dummy;
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if (mode == 1) {
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switch (led) {
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case 0:
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addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x08000);
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break;
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case 1:
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addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x0c000);
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break;
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case 2:
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addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x10000);
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break;
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}
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} else if (mode == 0) {
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switch (led) {
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case 0:
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addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x14000);
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break;
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case 1:
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addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x18000);
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break;
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case 2:
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addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x1c000);
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break;
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}
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}
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WRITE_CHAR(addr, 0);
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dummy = *addr;
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#endif /* CONFIG_ZUMA_V2 */
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}
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void
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display_mem_map(void)
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{
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int i,j;
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unsigned int base,size,width;
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/* SDRAM */
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printf("SDRAM\n");
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for(i=0;i<=BANK3;i++) {
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base = memoryGetBankBaseAddress(i);
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size = memoryGetBankSize(i);
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if(size !=0)
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{
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printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20);
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}
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}
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/* CPU's PCI windows */
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for(i=0;i<=PCI_HOST1;i++) {
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printf("\nCPU's PCI %d windows\n", i);
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base=pciGetSpaceBase(i,PCI_IO);
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size=pciGetSpaceSize(i,PCI_IO);
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printf(" IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20);
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for(j=0;j<=PCI_REGION3;j++) {
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base = pciGetSpaceBase(i,j);
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size = pciGetSpaceSize(i,j);
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printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base,
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size>>20);
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}
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}
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/* Devices */
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printf("\nDEVICES\n");
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for(i=0;i<=DEVICE3;i++) {
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base = memoryGetDeviceBaseAddress(i);
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size = memoryGetDeviceSize(i);
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width= memoryGetDeviceWidth(i) * 8;
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printf("DEV %d: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
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i, base, size>>20, width);
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}
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/* Bootrom */
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base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */
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size = memoryGetDeviceSize(BOOT_DEVICE);
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width= memoryGetDeviceWidth(BOOT_DEVICE) * 8;
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printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
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base, size>>20, width);
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}
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