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https://github.com/brain-hackers/u-boot-brain
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79c7a90f6c
This controller was introduced on Tegra114 to handle XUSB pads. On Tegra124 it is also used for PCIe and SATA pin muxing and PHY control. Only the Tegra124 PCIe and SATA functionality is currently implemented, with weak symbols on Tegra114. Tegra20 and Tegra30 also provide weak symbols for these functions so that drivers can use the same API irrespective of which SoC they're being built for. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
25 lines
830 B
C
25 lines
830 B
C
#ifndef _TEGRA_XUSB_PADCTL_H_
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#define _TEGRA_XUSB_PADCTL_H_
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struct tegra_xusb_phy;
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/**
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* tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY
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* @type: the type of PHY to obtain
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*
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* The type of PHY varies between SoC generations. Typically there are XUSB,
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* PCIe and SATA PHYs, though not all generations support all of them. The
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* value of type can usually be directly parsed from a device tree.
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*
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* Return: a pointer to the PHY or NULL if no such PHY exists
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*/
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struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
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void tegra_xusb_padctl_init(const void *fdt);
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int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
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int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
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int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
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int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy);
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#endif
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