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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Allow this to be used by other Tegra SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
138 lines
4.5 KiB
C
138 lines
4.5 KiB
C
/*
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* (C) Copyright 2010
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
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#define __ASM_ARCH_TEGRA_DISPLAY_H
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#include <asm/arch-tegra/dc.h>
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#include <fdtdec.h>
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#include <asm/gpio.h>
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/* This holds information about a window which can be displayed */
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struct disp_ctl_win {
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enum win_color_depth_id fmt; /* Color depth/format */
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unsigned bpp; /* Bits per pixel */
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phys_addr_t phys_addr; /* Physical address in memory */
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unsigned x; /* Horizontal address offset (bytes) */
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unsigned y; /* Veritical address offset (bytes) */
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unsigned w; /* Width of source window */
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unsigned h; /* Height of source window */
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unsigned stride; /* Number of bytes per line */
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unsigned out_x; /* Left edge of output window (col) */
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unsigned out_y; /* Top edge of output window (row) */
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unsigned out_w; /* Width of output window in pixels */
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unsigned out_h; /* Height of output window in pixels */
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};
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#define FDT_LCD_TIMINGS 4
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enum {
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FDT_LCD_TIMING_REF_TO_SYNC,
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FDT_LCD_TIMING_SYNC_WIDTH,
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FDT_LCD_TIMING_BACK_PORCH,
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FDT_LCD_TIMING_FRONT_PORCH,
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FDT_LCD_TIMING_COUNT,
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};
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enum lcd_cache_t {
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FDT_LCD_CACHE_OFF = 0,
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FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0,
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FDT_LCD_CACHE_WRITE_BACK = 1 << 1,
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FDT_LCD_CACHE_FLUSH = 1 << 2,
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FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK |
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FDT_LCD_CACHE_FLUSH,
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};
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/* Information about the display controller */
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struct fdt_disp_config {
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int valid; /* config is valid */
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int width; /* width in pixels */
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int height; /* height in pixels */
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int bpp; /* number of bits per pixel */
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/*
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* log2 of number of bpp, in general, unless it bpp is 24 in which
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* case this field holds 24 also! This is a U-Boot thing.
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*/
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int log2_bpp;
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struct disp_ctlr *disp; /* Display controller to use */
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fdt_addr_t frame_buffer; /* Address of frame buffer */
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unsigned pixel_clock; /* Pixel clock in Hz */
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uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */
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uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */
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int panel_node; /* node offset of panel information */
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};
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/* Information about the LCD panel */
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struct fdt_panel_config {
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int pwm_channel; /* PWM channel to use for backlight */
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enum lcd_cache_t cache_type;
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struct gpio_desc backlight_en; /* GPIO for backlight enable */
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struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */
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struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */
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struct gpio_desc panel_vdd; /* GPIO for panel vdd */
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/*
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* Panel required timings
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* Timing 1: delay between panel_vdd-rise and data-rise
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* Timing 2: delay between data-rise and backlight_vdd-rise
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* Timing 3: delay between backlight_vdd and pwm-rise
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* Timing 4: delay between pwm-rise and backlight_en-rise
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*/
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uint panel_timings[FDT_LCD_TIMINGS];
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};
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/**
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* Register a new display based on device tree configuration.
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*
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* The frame buffer can be positioned by U-Boot or overriden by the fdt.
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* You should pass in the U-Boot address here, and check the contents of
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* struct fdt_disp_config to see what was actually chosen.
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*
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* @param blob Device tree blob
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* @param default_lcd_base Default address of LCD frame buffer
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* @return 0 if ok, -1 on error (unsupported bits per pixel)
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*/
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int tegra_display_probe(const void *blob, void *default_lcd_base);
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/**
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* Return the current display configuration
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*
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* @return pointer to display configuration, or NULL if there is no valid
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* config
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*/
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struct fdt_disp_config *tegra_display_get_config(void);
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/**
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* Perform the next stage of the LCD init if it is time to do so.
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*
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* LCD init can be time-consuming because of the number of delays we need
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* while waiting for the backlight power supply, etc. This function can
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* be called at various times during U-Boot operation to advance the
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* initialization of the LCD to the next stage if sufficient time has
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* passed since the last stage. It keeps track of what stage it is up to
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* and the time that it is permitted to move to the next stage.
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*
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* The final call should have wait=1 to complete the init.
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*
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* @param blob fdt blob containing LCD information
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* @param wait 1 to wait until all init is complete, and then return
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* 0 to return immediately, potentially doing nothing if it is
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* not yet time for the next init.
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*/
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int tegra_lcd_check_next_stage(const void *blob, int wait);
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/**
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* Set up the maximum LCD size so we can size the frame buffer.
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*
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* @param blob fdt blob containing LCD information
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*/
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void tegra_lcd_early_init(const void *blob);
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#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
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