mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
286 lines
7.8 KiB
ArmAsm
286 lines
7.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Author: Hongbo Zhang <hongbo.zhang@nxp.com>
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* This file implements LS102X platform PSCI SYSTEM-SUSPEND function
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/psci.h>
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/* Default PSCI function, return -1, Not Implemented */
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#define PSCI_DEFAULT(__fn) \
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ENTRY(__fn); \
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mov w0, #ARM_PSCI_RET_NI; \
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ret; \
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ENDPROC(__fn); \
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.weak __fn
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/* PSCI function and ID table definition*/
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#define PSCI_TABLE(__id, __fn) \
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.word __id; \
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.word __fn
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.pushsection ._secure.text, "ax"
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/* 32 bits PSCI default functions */
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PSCI_DEFAULT(psci_version)
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PSCI_DEFAULT(psci_cpu_suspend)
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PSCI_DEFAULT(psci_cpu_off)
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PSCI_DEFAULT(psci_cpu_on)
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PSCI_DEFAULT(psci_affinity_info)
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PSCI_DEFAULT(psci_migrate)
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PSCI_DEFAULT(psci_migrate_info_type)
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PSCI_DEFAULT(psci_migrate_info_up_cpu)
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PSCI_DEFAULT(psci_system_off)
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PSCI_DEFAULT(psci_system_reset)
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PSCI_DEFAULT(psci_features)
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PSCI_DEFAULT(psci_cpu_freeze)
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PSCI_DEFAULT(psci_cpu_default_suspend)
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PSCI_DEFAULT(psci_node_hw_state)
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PSCI_DEFAULT(psci_system_suspend)
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PSCI_DEFAULT(psci_set_suspend_mode)
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PSCI_DEFAULT(psi_stat_residency)
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PSCI_DEFAULT(psci_stat_count)
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.align 3
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_psci_32_table:
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PSCI_TABLE(ARM_PSCI_FN_CPU_SUSPEND, psci_cpu_suspend)
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PSCI_TABLE(ARM_PSCI_FN_CPU_OFF, psci_cpu_off)
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PSCI_TABLE(ARM_PSCI_FN_CPU_ON, psci_cpu_on)
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PSCI_TABLE(ARM_PSCI_FN_MIGRATE, psci_migrate)
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PSCI_TABLE(ARM_PSCI_0_2_FN_PSCI_VERSION, psci_version)
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PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_SUSPEND, psci_cpu_suspend)
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PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_OFF, psci_cpu_off)
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PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_ON, psci_cpu_on)
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PSCI_TABLE(ARM_PSCI_0_2_FN_AFFINITY_INFO, psci_affinity_info)
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PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE, psci_migrate)
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PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE, psci_migrate_info_type)
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PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu)
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PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_OFF, psci_system_off)
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PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_RESET, psci_system_reset)
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PSCI_TABLE(ARM_PSCI_1_0_FN_PSCI_FEATURES, psci_features)
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PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_FREEZE, psci_cpu_freeze)
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PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend)
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PSCI_TABLE(ARM_PSCI_1_0_FN_NODE_HW_STATE, psci_node_hw_state)
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PSCI_TABLE(ARM_PSCI_1_0_FN_SYSTEM_SUSPEND, psci_system_suspend)
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PSCI_TABLE(ARM_PSCI_1_0_FN_SET_SUSPEND_MODE, psci_set_suspend_mode)
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PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_RESIDENCY, psi_stat_residency)
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PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_COUNT, psci_stat_count)
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PSCI_TABLE(0, 0)
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/* 64 bits PSCI default functions */
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PSCI_DEFAULT(psci_cpu_suspend_64)
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PSCI_DEFAULT(psci_cpu_on_64)
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PSCI_DEFAULT(psci_affinity_info_64)
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PSCI_DEFAULT(psci_migrate_64)
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PSCI_DEFAULT(psci_migrate_info_up_cpu_64)
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PSCI_DEFAULT(psci_cpu_default_suspend_64)
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PSCI_DEFAULT(psci_node_hw_state_64)
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PSCI_DEFAULT(psci_system_suspend_64)
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PSCI_DEFAULT(psci_stat_residency_64)
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PSCI_DEFAULT(psci_stat_count_64)
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.align 3
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_psci_64_table:
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PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_SUSPEND, psci_cpu_suspend_64)
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PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_ON, psci_cpu_on_64)
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PSCI_TABLE(ARM_PSCI_0_2_FN64_AFFINITY_INFO, psci_affinity_info_64)
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PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE, psci_migrate_64)
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PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu_64)
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PSCI_TABLE(ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend_64)
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PSCI_TABLE(ARM_PSCI_1_0_FN64_NODE_HW_STATE, psci_node_hw_state_64)
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PSCI_TABLE(ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND, psci_system_suspend_64)
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PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_RESIDENCY, psci_stat_residency_64)
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PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_COUNT, psci_stat_count_64)
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PSCI_TABLE(0, 0)
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.macro psci_enter
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/* PSCI call is Fast Call(atomic), so mask DAIF */
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mrs x15, DAIF
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stp x15, xzr, [sp, #-16]!
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ldr x15, =0x3C0
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msr DAIF, x15
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/* SMC convention, x18 ~ x30 should be saved by callee */
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stp x29, x30, [sp, #-16]!
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stp x27, x28, [sp, #-16]!
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stp x25, x26, [sp, #-16]!
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stp x23, x24, [sp, #-16]!
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stp x21, x22, [sp, #-16]!
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stp x19, x20, [sp, #-16]!
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mrs x15, elr_el3
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stp x18, x15, [sp, #-16]!
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.endm
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.macro psci_return
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/* restore registers */
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ldp x18, x15, [sp], #16
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msr elr_el3, x15
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ldp x19, x20, [sp], #16
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ldp x21, x22, [sp], #16
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ldp x23, x24, [sp], #16
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ldp x25, x26, [sp], #16
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ldp x27, x28, [sp], #16
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ldp x29, x30, [sp], #16
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/* restore DAIF */
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ldp x15, xzr, [sp], #16
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msr DAIF, x15
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eret
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.endm
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/* Caller must put PSCI function-ID table base in x9 */
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handle_psci:
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psci_enter
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1: ldr x10, [x9] /* Load PSCI function table */
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ubfx x11, x10, #32, #32
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ubfx x10, x10, #0, #32
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cbz x10, 3f /* If reach the end, bail out */
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cmp x10, x0
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b.eq 2f /* PSCI function found */
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add x9, x9, #8 /* If not match, try next entry */
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b 1b
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2: blr x11 /* Call PSCI function */
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psci_return
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3: mov x0, #ARM_PSCI_RET_NI
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psci_return
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unknown_smc_id:
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ldr x0, =0xFFFFFFFF
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eret
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handle_smc32:
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/* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */
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ldr w9, =0x8400001F
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cmp w0, w9
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b.gt unknown_smc_id
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ldr w9, =0x84000000
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cmp w0, w9
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b.lt unknown_smc_id
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adr x9, _psci_32_table
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b handle_psci
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handle_smc64:
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/* check SMC32 or SMC64 calls */
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ubfx x9, x0, #30, #1
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cbz x9, handle_smc32
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/* SMC function ID 0xC4000000-0xC400001F: 64 bits PSCI */
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ldr x9, =0xC400001F
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cmp x0, x9
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b.gt unknown_smc_id
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ldr x9, =0xC4000000
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cmp x0, x9
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b.lt unknown_smc_id
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adr x9, _psci_64_table
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b handle_psci
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/*
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* Get CPU ID from MPIDR, suppose every cluster has same number of CPU cores,
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* Platform with asymmetric clusters should implement their own interface.
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* In case this function being called by other platform's C code, the ARM
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* Architecture Procedure Call Standard is considered, e.g. register X0 is
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* used for the return value, while in this PSCI environment, X0 usually holds
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* the SMC function identifier, so X0 should be saved by caller function.
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*/
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ENTRY(psci_get_cpu_id)
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#ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
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mrs x9, MPIDR_EL1
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ubfx x9, x9, #8, #8
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ldr x10, =CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
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mul x9, x10, x9
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#else
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mov x9, xzr
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#endif
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mrs x10, MPIDR_EL1
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ubfx x10, x10, #0, #8
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add x0, x10, x9
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ret
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ENDPROC(psci_get_cpu_id)
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.weak psci_get_cpu_id
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/* CPU ID input in x0, stack top output in x0*/
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LENTRY(psci_get_cpu_stack_top)
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adr x9, __secure_stack_end
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lsl x0, x0, #ARM_PSCI_STACK_SHIFT
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sub x0, x9, x0
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ret
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ENDPROC(psci_get_cpu_stack_top)
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unhandled_exception:
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b unhandled_exception /* simply dead loop */
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handle_sync:
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mov x15, x30
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mov x14, x0
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bl psci_get_cpu_id
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bl psci_get_cpu_stack_top
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mov x9, #1
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msr spsel, x9
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mov sp, x0
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mov x0, x14
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mov x30, x15
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mrs x9, esr_el3
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ubfx x9, x9, #26, #6
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cmp x9, #0x13
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b.eq handle_smc32
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cmp x9, #0x17
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b.eq handle_smc64
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b unhandled_exception
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.align 11
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.globl el3_exception_vectors
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el3_exception_vectors:
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b unhandled_exception /* Sync, Current EL using SP0 */
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.align 7
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b unhandled_exception /* IRQ, Current EL using SP0 */
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.align 7
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b unhandled_exception /* FIQ, Current EL using SP0 */
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.align 7
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b unhandled_exception /* SError, Current EL using SP0 */
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.align 7
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b unhandled_exception /* Sync, Current EL using SPx */
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.align 7
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b unhandled_exception /* IRQ, Current EL using SPx */
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.align 7
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b unhandled_exception /* FIQ, Current EL using SPx */
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.align 7
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b unhandled_exception /* SError, Current EL using SPx */
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.align 7
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b handle_sync /* Sync, Lower EL using AArch64 */
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.align 7
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b unhandled_exception /* IRQ, Lower EL using AArch64 */
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.align 7
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b unhandled_exception /* FIQ, Lower EL using AArch64 */
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.align 7
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b unhandled_exception /* SError, Lower EL using AArch64 */
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.align 7
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b unhandled_exception /* Sync, Lower EL using AArch32 */
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.align 7
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b unhandled_exception /* IRQ, Lower EL using AArch32 */
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.align 7
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b unhandled_exception /* FIQ, Lower EL using AArch32 */
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.align 7
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b unhandled_exception /* SError, Lower EL using AArch32 */
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ENTRY(psci_setup_vectors)
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adr x0, el3_exception_vectors
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msr vbar_el3, x0
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ret
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ENDPROC(psci_setup_vectors)
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ENTRY(psci_arch_init)
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ret
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ENDPROC(psci_arch_init)
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.weak psci_arch_init
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.popsection
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