mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-03 16:53:44 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
92 lines
2.3 KiB
C
92 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/armada100.h>
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#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
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#define SET_MRVL_ID (1<<8)
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#define L2C_RAM_SEL (1<<4)
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int arch_cpu_init(void)
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{
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u32 val;
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struct armd1cpu_registers *cpuregs =
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(struct armd1cpu_registers *) ARMD1_CPU_BASE;
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struct armd1apb1_registers *apb1clkres =
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(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
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struct armd1mpmu_registers *mpmu =
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(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
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/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
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val = readl(&cpuregs->cpu_conf);
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val = val | SET_MRVL_ID;
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writel(val, &cpuregs->cpu_conf);
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/* Enable Clocks for all hardware units */
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writel(0xFFFFFFFF, &mpmu->acgr);
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/* Turn on AIB and AIB-APB Functional clock */
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writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
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/* ensure L2 cache is not mapped as SRAM */
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val = readl(&cpuregs->cpu_conf);
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val = val & ~(L2C_RAM_SEL);
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writel(val, &cpuregs->cpu_conf);
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/* Enable GPIO clock */
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writel(APBC_APBCLK, &apb1clkres->gpio);
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#ifdef CONFIG_I2C_MV
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/* Enable general I2C clock */
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writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
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writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
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/* Enable power I2C clock */
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writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
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writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
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#endif
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/*
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* Enable Functional and APB clock at 14.7456MHz
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* for configured UART console
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*/
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#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
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writel(UARTCLK14745KHZ, &apb1clkres->uart3);
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#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
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writel(UARTCLK14745KHZ, &apb1clkres->uart2);
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#else
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writel(UARTCLK14745KHZ, &apb1clkres->uart1);
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#endif
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icache_enable();
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return 0;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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u32 id;
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struct armd1cpu_registers *cpuregs =
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(struct armd1cpu_registers *) ARMD1_CPU_BASE;
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id = readl(&cpuregs->chip_id);
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printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
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return 0;
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}
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#endif
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#ifdef CONFIG_I2C_MV
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void i2c_clk_enable(void)
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{
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}
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#endif
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