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6912f2a8ae
This patch disables DM watchdog support for SPL builds and uses the legacy omap watchdog driver on TI AM335x chipsets. The following build error is reported if DM watchdog support was enabled in SPL: CC spl/drivers/usb/gadget/rndis.o LD spl/drivers/usb/gadget/built-in.o LD spl/drivers/usb/musb-new/built-in.o LD spl/drivers/built-in.o LD spl/u-boot-spl arm-linux-ld.bfd: u-boot-spl section .u_boot_list will not fit in region .sram arm-linux-ld.bfd: region .sram overflowed by 440 bytes make[1]: *** [spl/u-boot-spl] Error 1 make: *** [spl/u-boot-spl] Error 2 Adjusted WATCHDOG_RESET macro accordingly. Earlier it was pointing to hw_watchdog_reset. Since CONFIG_WATCHDOG replaces CONFIG_HW_WATCHDOG, now WATCHDOG_RESET macro points to watchdog_reset. This watchdog_reset is not defined anywhere for am33xx/omap2 and needs to be defined. Fixed this by simply calling hw_watchdog_reset in watchdog_reset. Built and tested on AM335x device (BeagleboneBlack), compile tested for all other AM33xx/omap2 based boards. Signed-off-by: Suniel Mahesh <sunil.m@techveda.org> [trini: Fix watchdog.h logic] Signed-off-by: Tom Rini <trini@konsulko.com>
258 lines
6.4 KiB
C
258 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* omap_wdt.c
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*
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* (C) Copyright 2013
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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*
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* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
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*
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* commit 2d991a164a61858012651e13c59521975504e260
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* Author: Bill Pemberton <wfp5p@virginia.edu>
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* Date: Mon Nov 19 13:21:41 2012 -0500
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*
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* watchdog: remove use of __devinit
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*
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* CONFIG_HOTPLUG is going away as an option so __devinit is no longer
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* needed.
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*
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* Author: MontaVista Software, Inc.
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* <gdavis@mvista.com> or <source@mvista.com>
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*
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* History:
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*
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* 20030527: George G. Davis <gdavis@mvista.com>
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* Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
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* (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
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* Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
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*
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* Copyright (c) 2004 Texas Instruments.
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* 1. Modified to support OMAP1610 32-KHz watchdog timer
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* 2. Ported to 2.6 kernel
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*
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* Copyright (c) 2005 David Brownell
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* Use the driver model and standard identifiers; handle bigger timeouts.
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/cpu.h>
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#include <wdt.h>
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#include <dm.h>
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#include <errno.h>
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/* Hardware timeout in seconds */
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#define WDT_HW_TIMEOUT 60
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#if !CONFIG_IS_ENABLED(WDT)
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static unsigned int wdt_trgr_pattern = 0x1234;
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void hw_watchdog_reset(void)
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{
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struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
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/*
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* Somebody just triggered watchdog reset and write to WTGR register
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* is in progress. It is resetting right now, no need to trigger it
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* again
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*/
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if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
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return;
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wdt_trgr_pattern = ~wdt_trgr_pattern;
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writel(wdt_trgr_pattern, &wdt->wdtwtgr);
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/*
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* Don't wait for posted write to complete, i.e. don't check
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* WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
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* WTGR register outside of this func, and if entering it
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* we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
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* was just triggered. This prevents us from wasting time in busy
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* polling of WDT_WWPS_PEND_WTGR bit.
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*/
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}
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static int omap_wdt_set_timeout(unsigned int timeout)
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{
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struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
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u32 pre_margin = GET_WLDR_VAL(timeout);
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/* just count up at 32 KHz */
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while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
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;
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writel(pre_margin, &wdt->wdtwldr);
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while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
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;
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return 0;
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}
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void hw_watchdog_disable(void)
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{
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struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
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/*
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* Disable watchdog
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*/
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writel(0xAAAA, &wdt->wdtwspr);
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while (readl(&wdt->wdtwwps) != 0x0)
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;
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writel(0x5555, &wdt->wdtwspr);
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while (readl(&wdt->wdtwwps) != 0x0)
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;
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}
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void hw_watchdog_init(void)
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{
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struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
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/*
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* Make sure the watchdog is disabled. This is unfortunately required
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* because writing to various registers with the watchdog running has no
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* effect.
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*/
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hw_watchdog_disable();
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/* initialize prescaler */
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while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
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;
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writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr);
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while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
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;
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omap_wdt_set_timeout(WDT_HW_TIMEOUT);
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/* Sequence to enable the watchdog */
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writel(0xBBBB, &wdt->wdtwspr);
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while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
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;
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writel(0x4444, &wdt->wdtwspr);
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while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
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;
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}
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void watchdog_reset(void)
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{
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hw_watchdog_reset();
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}
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#else
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static int omap3_wdt_reset(struct udevice *dev)
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{
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struct omap3_wdt_priv *priv = dev_get_priv(dev);
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priv->wdt_trgr_pattern = 0x1234;
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/*
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* Somebody just triggered watchdog reset and write to WTGR register
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* is in progress. It is resetting right now, no need to trigger it
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* again
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*/
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if ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
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return 0;
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priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
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writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
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/*
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* Don't wait for posted write to complete, i.e. don't check
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* WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
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* WTGR register outside of this func, and if entering it
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* we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
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* was just triggered. This prevents us from wasting time in busy
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* polling of WDT_WWPS_PEND_WTGR bit.
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*/
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return 0;
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}
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static int omap3_wdt_stop(struct udevice *dev)
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{
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struct omap3_wdt_priv *priv = dev_get_priv(dev);
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/* disable watchdog */
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writel(0xAAAA, &priv->regs->wdtwspr);
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while (readl(&priv->regs->wdtwwps) != 0x0)
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;
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writel(0x5555, &priv->regs->wdtwspr);
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while (readl(&priv->regs->wdtwwps) != 0x0)
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;
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return 0;
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}
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static int omap3_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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struct omap3_wdt_priv *priv = dev_get_priv(dev);
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u32 pre_margin = GET_WLDR_VAL(timeout_ms);
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/*
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* Make sure the watchdog is disabled. This is unfortunately required
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* because writing to various registers with the watchdog running has no
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* effect.
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*/
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omap3_wdt_stop(dev);
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/* initialize prescaler */
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while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
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;
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writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &priv->regs->wdtwclr);
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while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WCLR)
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;
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/* just count up at 32 KHz */
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while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
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;
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writel(pre_margin, &priv->regs->wdtwldr);
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while (readl(&priv->regs->wdtwwps) & WDT_WWPS_PEND_WLDR)
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;
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/* Sequence to enable the watchdog */
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writel(0xBBBB, &priv->regs->wdtwspr);
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while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
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;
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writel(0x4444, &priv->regs->wdtwspr);
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while ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WSPR)
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;
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return 0;
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}
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static int omap3_wdt_probe(struct udevice *dev)
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{
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struct omap3_wdt_priv *priv = dev_get_priv(dev);
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priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
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if (!priv->regs)
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return -EINVAL;
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debug("%s: Probing wdt%u\n", __func__, dev->seq);
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return 0;
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}
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static const struct wdt_ops omap3_wdt_ops = {
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.start = omap3_wdt_start,
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.stop = omap3_wdt_stop,
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.reset = omap3_wdt_reset,
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};
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static const struct udevice_id omap3_wdt_ids[] = {
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{ .compatible = "ti,omap3-wdt" },
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{ }
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};
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U_BOOT_DRIVER(omap3_wdt) = {
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.name = "omap3_wdt",
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.id = UCLASS_WDT,
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.of_match = omap3_wdt_ids,
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.ops = &omap3_wdt_ops,
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.probe = omap3_wdt_probe,
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.priv_auto_alloc_size = sizeof(struct omap3_wdt_priv),
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};
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#endif /* !CONFIG_IS_ENABLED(WDT) */
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