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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
253 lines
6.4 KiB
C
253 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <irq_func.h>
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#include <mpc8xx.h>
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#include <mpc8xx_irq.h>
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#include <time.h>
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#include <asm/cpm_8xx.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ptrace.h>
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/************************************************************************/
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/*
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* CPM interrupt vector functions.
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*/
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struct interrupt_action {
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interrupt_handler_t *handler;
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void *arg;
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};
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static struct interrupt_action cpm_vecs[CPMVEC_NR];
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static struct interrupt_action irq_vecs[NR_IRQS];
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static void cpm_interrupt_init(void);
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static void cpm_interrupt(void *regs);
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/************************************************************************/
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void interrupt_init_cpu(unsigned *decrementer_count)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
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/* disable all interrupts */
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out_be32(&immr->im_siu_conf.sc_simask, 0);
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/* Configure CPM interrupts */
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cpm_interrupt_init();
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}
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/************************************************************************/
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/*
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* Handle external interrupts
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*/
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void external_interrupt(struct pt_regs *regs)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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int irq;
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ulong simask;
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ulong vec, v_bit;
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/*
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* read the SIVEC register and shift the bits down
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* to get the irq number
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*/
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vec = in_be32(&immr->im_siu_conf.sc_sivec);
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irq = vec >> 26;
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v_bit = 0x80000000UL >> irq;
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/*
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* Read Interrupt Mask Register and Mask Interrupts
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*/
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simask = in_be32(&immr->im_siu_conf.sc_simask);
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clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);
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if (!(irq & 0x1)) { /* External Interrupt ? */
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ulong siel;
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/*
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* Read Interrupt Edge/Level Register
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*/
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siel = in_be32(&immr->im_siu_conf.sc_siel);
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if (siel & v_bit) { /* edge triggered interrupt ? */
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/*
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* Rewrite SIPEND Register to clear interrupt
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*/
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out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
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}
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}
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if (irq_vecs[irq].handler != NULL) {
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irq_vecs[irq].handler(irq_vecs[irq].arg);
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} else {
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printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
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irq, vec);
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/* turn off the bogus interrupt to avoid it from now */
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simask &= ~v_bit;
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}
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/*
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* Re-Enable old Interrupt Mask
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*/
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out_be32(&immr->im_siu_conf.sc_simask, simask);
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}
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/************************************************************************/
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/*
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* CPM interrupt handler
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*/
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static void cpm_interrupt(void *regs)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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uint vec;
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/*
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* Get the vector by setting the ACK bit
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* and then reading the register.
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*/
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out_be16(&immr->im_cpic.cpic_civr, 1);
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vec = in_be16(&immr->im_cpic.cpic_civr);
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vec >>= 11;
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if (cpm_vecs[vec].handler != NULL) {
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(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
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} else {
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clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
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printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
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}
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/*
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* After servicing the interrupt,
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* we have to remove the status indicator.
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*/
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setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
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}
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/*
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* The CPM can generate the error interrupt when there is a race
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* condition between generating and masking interrupts. All we have
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* to do is ACK it and return. This is a no-op function so we don't
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* need any special tests in the interrupt handler.
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*/
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static void cpm_error_interrupt(void *dummy)
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{
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}
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/************************************************************************/
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/*
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* Install and free an interrupt handler
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*/
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void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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if ((vec & CPMVEC_OFFSET) != 0) {
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/* CPM interrupt */
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vec &= 0xffff;
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if (cpm_vecs[vec].handler != NULL)
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printf("CPM interrupt 0x%x replacing 0x%x\n",
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(uint)handler, (uint)cpm_vecs[vec].handler);
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cpm_vecs[vec].handler = handler;
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cpm_vecs[vec].arg = arg;
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setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
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} else {
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/* SIU interrupt */
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if (irq_vecs[vec].handler != NULL)
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printf("SIU interrupt %d 0x%x replacing 0x%x\n",
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vec, (uint)handler, (uint)cpm_vecs[vec].handler);
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irq_vecs[vec].handler = handler;
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irq_vecs[vec].arg = arg;
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setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
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}
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}
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void irq_free_handler(int vec)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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if ((vec & CPMVEC_OFFSET) != 0) {
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/* CPM interrupt */
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vec &= 0xffff;
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clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
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cpm_vecs[vec].handler = NULL;
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cpm_vecs[vec].arg = NULL;
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} else {
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/* SIU interrupt */
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clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
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irq_vecs[vec].handler = NULL;
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irq_vecs[vec].arg = NULL;
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}
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}
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/************************************************************************/
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static void cpm_interrupt_init(void)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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uint cicr;
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/*
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* Initialize the CPM interrupt controller.
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*/
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cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
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((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
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out_be32(&immr->im_cpic.cpic_cicr, cicr);
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out_be32(&immr->im_cpic.cpic_cimr, 0);
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/*
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* Install the error handler.
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*/
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irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
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setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
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/*
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* Install the cpm interrupt handler
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*/
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irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
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}
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/************************************************************************/
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/*
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* timer_interrupt - gets called when the decrementer overflows,
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* with interrupts disabled.
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* Trivial implementation - no need to be really accurate.
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*/
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void timer_interrupt_cpu(struct pt_regs *regs)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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/* Reset Timer Expired and Timers Interrupt Status */
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out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
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__asm__ ("nop");
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/*
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Clear TEXPS (and TMIST on older chips). SPLSS (on older
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chips) is cleared too.
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Bitwise OR is a read-modify-write operation so ALL bits
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which are cleared by writing `1' would be cleared by
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operations like
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immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
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The same can be achieved by simple writing of the PLPRCR
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to itself. If a bit value should be preserved, read the
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register, ZERO the bit and write, not OR, the result back.
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*/
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setbits_be32(&immr->im_clkrst.car_plprcr, 0);
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}
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/************************************************************************/
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