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![Andre Przywara](/assets/img/avatar_default.png)
Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM. Split the timing parameters for this LPDDR3 configuration into a separate file, to allow selecting an alternative later at compile time (as the sunxi-dw driver does). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
133 lines
3.9 KiB
C
133 lines
3.9 KiB
C
/*
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* sun50i H6 LPDDR3 timings
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*
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* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/cpu.h>
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static u32 mr_lpddr3[12] = {
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0x00000000, 0x00000043, 0x0000001a, 0x00000001,
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0x00000000, 0x00000000, 0x00000048, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x00000003,
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};
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/* TODO: flexible timing */
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void mctl_set_timing_params(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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struct sunxi_mctl_phy_reg * const mctl_phy =
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(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
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int i;
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u8 tccd = 2;
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u8 tfaw = max(ns_to_t(50), 4);
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u8 trrd = max(ns_to_t(10), 2);
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u8 trcd = max(ns_to_t(24), 2);
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u8 trc = ns_to_t(70);
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u8 txp = max(ns_to_t(8), 2);
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u8 twtr = max(ns_to_t(8), 2);
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u8 trtp = max(ns_to_t(8), 2);
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u8 twr = max(ns_to_t(15), 2);
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u8 trp = ns_to_t(18);
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u8 tras = ns_to_t(42);
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u8 twtr_sa = ns_to_t(5);
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u8 tcksrea = ns_to_t(11);
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u16 trefi = ns_to_t(3900) / 32;
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u16 trfc = ns_to_t(210);
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u16 txsr = ns_to_t(220);
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if (CONFIG_DRAM_CLK % 400 == 0) {
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/* Round up these parameters */
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twtr_sa++;
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tcksrea++;
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}
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u8 tmrw = 5;
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u8 tmrd = 5;
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u8 tmod = 12;
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u8 tcke = 3;
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u8 tcksrx = 5;
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u8 tcksre = 5;
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u8 tckesr = 5;
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u8 trasmax = CONFIG_DRAM_CLK / 60;
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u8 txs = 4;
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u8 txsdll = 4;
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u8 txsabort = 4;
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u8 txsfast = 4;
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u8 tcl = 5; /* CL 10 */
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u8 tcwl = 3; /* CWL 6 */
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u8 t_rdata_en = twtr_sa + 8;
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u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
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u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
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u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */
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u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
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u8 twtp = tcwl + 4 + twr + 1;
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/*
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* The code below for twr2rd and trd2wr follows the IP core's
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* document from ZynqMP and i.MX7. The BSP has both number
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* substracted by 2.
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*/
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u8 twr2rd = tcwl + 4 + 1 + twtr;
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u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1;
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/* set mode registers */
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for (i = 0; i < ARRAY_SIZE(mr_lpddr3); i++)
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writel(mr_lpddr3[i], &mctl_phy->mr[i]);
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/* set DRAM timing */
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writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
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&mctl_ctl->dramtmg[0]);
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writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
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writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
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&mctl_ctl->dramtmg[2]);
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writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
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writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
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&mctl_ctl->dramtmg[4]);
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writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
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&mctl_ctl->dramtmg[5]);
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/* Value suggested by ZynqMP manual and used by libdram */
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writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
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writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
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&mctl_ctl->dramtmg[8]);
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writel(txsr, &mctl_ctl->dramtmg[14]);
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clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));
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writel(0, &mctl_ctl->dfimisc);
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clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
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/*
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* Set timing registers of the PHY.
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* Note: the PHY is clocked 2x from the DRAM frequency.
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*/
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writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),
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&mctl_phy->dtpr[0]);
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writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);
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writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);
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writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),
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&mctl_phy->dtpr[3]);
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writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);
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writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
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writel(0x0505, &mctl_phy->dtpr[6]);
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/* Configure DFI timing */
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writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000,
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&mctl_ctl->dfitmg0);
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writel(0x040201, &mctl_ctl->dfitmg1);
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/* Configure PHY timing */
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writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);
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writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);
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/* set refresh timing */
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writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
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}
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