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https://github.com/brain-hackers/u-boot-brain
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313 lines
8.0 KiB
C
313 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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#include <hang.h>
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#include <log.h>
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#include <asm/utils.h>
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#include <asm/arch/dra7xx_iodelay.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mux_dra7xx.h>
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#include <asm/omap_common.h>
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static int isolate_io(u32 isolate)
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{
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if (isolate) {
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clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ,
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SDCARD_PWRDNZ);
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clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ,
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SDCARD_BIAS_PWRDNZ);
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}
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/* Override control on ISOCLKIN signal to IO pad ring. */
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clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
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PMCTRL_ISOCLK_OVERRIDE_CTRL);
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if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK,
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(u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
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return ERR_DEISOLATE_IO << isolate;
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/* Isolate/Deisolate IO */
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clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK,
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isolate << CTRL_ISOLATE_SHIFT);
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/* Dummy read to add delay t > 10ns */
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readl((*ctrl)->ctrl_core_sma_sw_0);
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/* Return control on ISOCLKIN to hardware */
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clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
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PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL);
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if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK,
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0 << PMCTRL_ISOCLK_STATUS_SHIFT,
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(u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
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return ERR_DEISOLATE_IO << isolate;
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return 0;
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}
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static int calibrate_iodelay(u32 base)
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{
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u32 reg;
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/* Configure REFCLK period */
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reg = readl(base + CFG_REG_2_OFFSET);
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reg &= ~CFG_REG_REFCLK_PERIOD_MASK;
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reg |= CFG_REG_REFCLK_PERIOD;
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writel(reg, base + CFG_REG_2_OFFSET);
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/* Initiate Calibration */
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clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK,
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CFG_REG_CALIB_STRT << CFG_REG_CALIB_STRT_SHIFT);
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if (!wait_on_value(CFG_REG_CALIB_STRT_MASK, CFG_REG_CALIB_END,
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(u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
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return ERR_CALIBRATE_IODELAY;
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return 0;
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}
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static int update_delay_mechanism(u32 base)
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{
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/* Initiate the reload of calibrated values. */
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clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK,
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CFG_REG_ROM_READ_START);
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if (!wait_on_value(CFG_REG_ROM_READ_MASK, CFG_REG_ROM_READ_END,
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(u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
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return ERR_UPDATE_DELAY;
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return 0;
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}
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static u32 calculate_delay(u32 base, u16 offset, u16 den)
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{
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u16 refclk_period, dly_cnt, ref_cnt;
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u32 reg, q, r;
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refclk_period = readl(base + CFG_REG_2_OFFSET) &
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CFG_REG_REFCLK_PERIOD_MASK;
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reg = readl(base + offset);
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dly_cnt = (reg & CFG_REG_DLY_CNT_MASK) >> CFG_REG_DLY_CNT_SHIFT;
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ref_cnt = (reg & CFG_REG_REF_CNT_MASK) >> CFG_REG_REF_CNT_SHIFT;
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if (!dly_cnt || !den)
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return 0;
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/*
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* To avoid overflow and integer truncation, delay value
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* is calculated as quotient + remainder.
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*/
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q = 5 * ((ref_cnt * refclk_period) / (dly_cnt * den));
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r = (10 * ((ref_cnt * refclk_period) % (dly_cnt * den))) /
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(2 * dly_cnt * den);
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return q + r;
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}
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static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde)
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{
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u32 g_delay_coarse, g_delay_fine;
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u32 a_delay_coarse, a_delay_fine;
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u32 c_elements, f_elements;
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u32 total_delay, reg = 0;
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g_delay_coarse = g_delay / 920;
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g_delay_fine = ((g_delay % 920) * 10) / 60;
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a_delay_coarse = a_delay / cpde;
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a_delay_fine = ((a_delay % cpde) * 10) / fpde;
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c_elements = g_delay_coarse + a_delay_coarse;
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f_elements = (g_delay_fine + a_delay_fine) / 10;
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if (f_elements > 22) {
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total_delay = c_elements * cpde + f_elements * fpde;
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c_elements = total_delay / cpde;
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f_elements = (total_delay % cpde) / fpde;
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}
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reg = (c_elements << CFG_X_COARSE_DLY_SHIFT) & CFG_X_COARSE_DLY_MASK;
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reg |= (f_elements << CFG_X_FINE_DLY_SHIFT) & CFG_X_FINE_DLY_MASK;
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reg |= CFG_X_SIGNATURE << CFG_X_SIGNATURE_SHIFT;
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reg |= CFG_X_LOCK << CFG_X_LOCK_SHIFT;
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return reg;
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}
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int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
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int niodelays)
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{
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struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array;
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u32 reg, cpde, fpde, i;
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if (!niodelays)
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return 0;
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cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET,
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88);
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if (!cpde)
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return ERR_CPDE;
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fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET,
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264);
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if (!fpde)
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return ERR_FPDE;
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for (i = 0; i < niodelays; i++, iodelay++) {
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reg = get_cfg_reg(iodelay->a_delay, iodelay->g_delay, cpde,
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fpde);
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writel(reg, base + iodelay->offset);
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}
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return 0;
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}
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int __recalibrate_iodelay_start(void)
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{
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int ret = 0;
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/* IO recalibration should be done only from SRAM */
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if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
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puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
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return -1;
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}
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/* unlock IODELAY CONFIG registers */
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writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
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CFG_REG_8_OFFSET);
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ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
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if (ret)
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goto err;
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ret = isolate_io(ISOLATE_IO);
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if (ret)
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goto err;
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ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
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err:
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return ret;
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}
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void __recalibrate_iodelay_end(int ret)
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{
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/* IO recalibration should be done only from SRAM */
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if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
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puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
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return;
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}
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/* Deisolate IO if it is already isolated */
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if (readl((*ctrl)->ctrl_core_sma_sw_0) & CTRL_ISOLATE_MASK)
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isolate_io(DEISOLATE_IO);
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/* lock IODELAY CONFIG registers */
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writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
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CFG_REG_8_OFFSET);
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/*
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* UART cannot be used during IO recalibration sequence as IOs are in
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* isolation. So error handling and debug prints are done after
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* complete IO delay recalibration sequence
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*/
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switch (ret) {
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case ERR_CALIBRATE_IODELAY:
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puts("IODELAY: IO delay calibration sequence failed\n");
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break;
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case ERR_ISOLATE_IO:
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puts("IODELAY: Isolation of Device IOs failed\n");
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break;
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case ERR_UPDATE_DELAY:
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puts("IODELAY: Delay mechanism update with new calibrated values failed\n");
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break;
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case ERR_DEISOLATE_IO:
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puts("IODELAY: De-isolation of Device IOs failed\n");
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break;
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case ERR_CPDE:
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puts("IODELAY: CPDE calculation failed\n");
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break;
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case ERR_FPDE:
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puts("IODELAY: FPDE calculation failed\n");
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break;
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case -1:
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puts("IODELAY: Wrong Context call?\n");
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break;
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default:
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debug("IODELAY: IO delay recalibration successfully completed\n");
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}
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/* If there is an error during iodelay recalibration, SoC is in a bad
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* state. Do not progress any further.
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*/
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if (ret)
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hang();
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return;
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}
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void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
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struct iodelay_cfg_entry const *iodelay,
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int niodelays)
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{
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int ret = 0;
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/* IO recalibration should be done only from SRAM */
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if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
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puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
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return;
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}
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ret = __recalibrate_iodelay_start();
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if (ret)
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goto err;
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/* Configure Mux settings */
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do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
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/* Configure Manual IO timing modes */
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ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
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if (ret)
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goto err;
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err:
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__recalibrate_iodelay_end(ret);
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}
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void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
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struct iodelay_cfg_entry const *iodelay,
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int niodelays)
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{
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int ret = 0;
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/* unlock IODELAY CONFIG registers */
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writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
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CFG_REG_8_OFFSET);
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ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
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if (ret)
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goto err;
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ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
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/* Configure Mux settings */
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do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
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/* Configure Manual IO timing modes */
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ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
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if (ret)
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goto err;
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err:
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/* lock IODELAY CONFIG registers */
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writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
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CFG_REG_8_OFFSET);
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}
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