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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
252 lines
5.9 KiB
C
252 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* clock_am43xx.c
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*
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* clocks for AM43XX based boards
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* Derived from AM33XX based boards
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
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struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
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struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
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const struct dpll_regs dpll_mpu_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x560,
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.cm_idlest_dpll = CM_WKUP + 0x564,
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.cm_clksel_dpll = CM_WKUP + 0x56c,
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.cm_div_m2_dpll = CM_WKUP + 0x570,
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};
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const struct dpll_regs dpll_core_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x520,
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.cm_idlest_dpll = CM_WKUP + 0x524,
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.cm_clksel_dpll = CM_WKUP + 0x52C,
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.cm_div_m4_dpll = CM_WKUP + 0x538,
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.cm_div_m5_dpll = CM_WKUP + 0x53C,
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.cm_div_m6_dpll = CM_WKUP + 0x540,
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};
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const struct dpll_regs dpll_per_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x5E0,
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.cm_idlest_dpll = CM_WKUP + 0x5E4,
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.cm_clksel_dpll = CM_WKUP + 0x5EC,
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.cm_div_m2_dpll = CM_WKUP + 0x5F0,
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};
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const struct dpll_regs dpll_ddr_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x5A0,
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.cm_idlest_dpll = CM_WKUP + 0x5A4,
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.cm_clksel_dpll = CM_WKUP + 0x5AC,
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.cm_div_m2_dpll = CM_WKUP + 0x5B0,
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.cm_div_m4_dpll = CM_WKUP + 0x5B8,
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};
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void setup_clocks_for_console(void)
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{
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u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
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/* Do not add any spl_debug prints in this function */
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clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
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CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
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CD_CLKCTRL_CLKTRCTRL_SHIFT);
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/* Enable UART0 */
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clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
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MODULE_CLKCTRL_MODULEMODE_MASK,
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MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
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MODULE_CLKCTRL_MODULEMODE_SHIFT);
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while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
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(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
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clkctrl = readl(&cmwkup->wkup_uart0ctrl);
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idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
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MODULE_CLKCTRL_IDLEST_SHIFT;
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}
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}
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void enable_basic_clocks(void)
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{
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u32 *const clk_domains[] = {
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&cmper->l3clkstctrl,
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&cmper->l3sclkstctrl,
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&cmper->l4lsclkstctrl,
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&cmwkup->wkclkstctrl,
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&cmper->emifclkstctrl,
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0
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};
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u32 *const clk_modules_explicit_en[] = {
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&cmper->l3clkctrl,
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&cmper->l4lsclkctrl,
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&cmper->l4fwclkctrl,
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&cmwkup->wkl4wkclkctrl,
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&cmper->l3instrclkctrl,
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&cmper->l4hsclkctrl,
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&cmwkup->wkgpio0clkctrl,
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&cmwkup->wkctrlclkctrl,
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&cmper->timer2clkctrl,
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&cmper->gpmcclkctrl,
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&cmper->elmclkctrl,
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&cmper->mmc0clkctrl,
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&cmper->mmc1clkctrl,
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&cmwkup->wkup_i2c0ctrl,
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&cmper->gpio1clkctrl,
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&cmper->gpio2clkctrl,
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&cmper->gpio3clkctrl,
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&cmper->gpio4clkctrl,
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&cmper->gpio5clkctrl,
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&cmper->i2c1clkctrl,
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&cmper->cpgmac0clkctrl,
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&cmper->emiffwclkctrl,
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&cmper->emifclkctrl,
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&cmper->otfaemifclkctrl,
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&cmper->qspiclkctrl,
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&cmper->spi0clkctrl,
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0
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};
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do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
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/* Select the Master osc clk as Timer2 clock source */
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writel(0x1, &cmdpll->clktimer2clk);
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/* For OPP100 the mac clock should be /5. */
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writel(0x4, &cmdpll->clkselmacclk);
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}
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void rtc_only_enable_basic_clocks(void)
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{
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u32 *const clk_domains[] = {
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&cmper->emifclkstctrl,
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0
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};
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u32 *const clk_modules_explicit_en[] = {
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&cmper->gpio5clkctrl,
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&cmper->emiffwclkctrl,
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&cmper->emifclkctrl,
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&cmper->otfaemifclkctrl,
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0
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};
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do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
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/* Select the Master osc clk as Timer2 clock source */
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writel(0x1, &cmdpll->clktimer2clk);
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}
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#ifdef CONFIG_TI_EDMA3
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void enable_edma3_clocks(void)
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{
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u32 *const clk_domains_edma3[] = {
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0
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};
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u32 *const clk_modules_explicit_en_edma3[] = {
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&cmper->tpccclkctrl,
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&cmper->tptc0clkctrl,
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0
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};
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do_enable_clocks(clk_domains_edma3,
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clk_modules_explicit_en_edma3,
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1);
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}
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void disable_edma3_clocks(void)
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{
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u32 *const clk_domains_edma3[] = {
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0
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};
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u32 *const clk_modules_disable_edma3[] = {
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&cmper->tpccclkctrl,
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&cmper->tptc0clkctrl,
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0
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};
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do_disable_clocks(clk_domains_edma3,
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clk_modules_disable_edma3,
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1);
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}
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#endif
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#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
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void enable_usb_clocks(int index)
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{
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u32 *usbclkctrl = 0;
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u32 *usbphyocp2scpclkctrl = 0;
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if (index == 0) {
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usbclkctrl = &cmper->usb0clkctrl;
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usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
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setbits_le32(&cmper->usb0clkctrl,
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USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
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setbits_le32(&cmwkup->usbphy0clkctrl,
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USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
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} else if (index == 1) {
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usbclkctrl = &cmper->usb1clkctrl;
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usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
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setbits_le32(&cmper->usb1clkctrl,
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USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
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setbits_le32(&cmwkup->usbphy1clkctrl,
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USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
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}
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u32 *const clk_domains_usb[] = {
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0
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};
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u32 *const clk_modules_explicit_en_usb[] = {
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usbclkctrl,
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usbphyocp2scpclkctrl,
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0
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};
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do_enable_clocks(clk_domains_usb, clk_modules_explicit_en_usb, 1);
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}
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void disable_usb_clocks(int index)
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{
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u32 *usbclkctrl = 0;
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u32 *usbphyocp2scpclkctrl = 0;
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if (index == 0) {
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usbclkctrl = &cmper->usb0clkctrl;
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usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
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clrbits_le32(&cmper->usb0clkctrl,
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USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
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clrbits_le32(&cmwkup->usbphy0clkctrl,
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USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
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} else if (index == 1) {
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usbclkctrl = &cmper->usb1clkctrl;
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usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
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clrbits_le32(&cmper->usb1clkctrl,
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USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
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clrbits_le32(&cmwkup->usbphy1clkctrl,
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USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
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}
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u32 *const clk_domains_usb[] = {
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0
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};
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u32 *const clk_modules_disable_usb[] = {
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usbclkctrl,
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usbphyocp2scpclkctrl,
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0
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};
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do_disable_clocks(clk_domains_usb, clk_modules_disable_usb, 1);
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}
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#endif
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