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https://github.com/brain-hackers/u-boot-brain
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786e8f818c
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask, it is never cleared, even if switching to DDR mode fails, and if the controller driver uses this flag to check the DDR mode, it can take incorrect actions. Also, DDR related checks in mmc_startup() incorrectly handle the case when the host controller does not support some bus widths (e.g. can't support 8 bits), since the host_caps is checked for DDR bit, but not bus width bits. This fix clearly separates using of card_caps bitmask, having there the flags for the capabilities, that the card can support, and actual operation mode, described outside of card_caps (i.e. bus_width and ddr_mode fields in mmc structure). Separate host controller drivers may need to be updated to use the actual flags. Respectively, the capabilities checks in mmc_startup are made more correct and clear. Also, some clean up is made with errors handling and code syntax layout. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> |
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| .. | ||
| arm_pl180_mmci.c | ||
| arm_pl180_mmci.h | ||
| bcm2835_sdhci.c | ||
| bfin_sdh.c | ||
| davinci_mmc.c | ||
| dw_mmc.c | ||
| exynos_dw_mmc.c | ||
| fsl_esdhc_spl.c | ||
| fsl_esdhc.c | ||
| ftsdc010_mci.c | ||
| ftsdc021_sdhci.c | ||
| gen_atmel_mci.c | ||
| Kconfig | ||
| kona_sdhci.c | ||
| Makefile | ||
| mmc_private.h | ||
| mmc_spi.c | ||
| mmc_write.c | ||
| mmc.c | ||
| mv_sdhci.c | ||
| mvebu_mmc.c | ||
| mxcmmc.c | ||
| mxsmmc.c | ||
| omap_hsmmc.c | ||
| pxa_mmc_gen.c | ||
| rpmb.c | ||
| s3c_sdi.c | ||
| s5p_sdhci.c | ||
| sdhci.c | ||
| sh_mmcif.c | ||
| sh_mmcif.h | ||
| socfpga_dw_mmc.c | ||
| spear_sdhci.c | ||
| sunxi_mmc.c | ||
| tegra_mmc.c | ||
| zynq_sdhci.c | ||