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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 21:33:24 +09:00
![Heinrich Schuchardt](/assets/img/avatar_default.png)
EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the EFI service ResetSystem. The missing definition is added. The value has to handled in efi_reset_system(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
947 lines
24 KiB
C
947 lines
24 KiB
C
/*
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* Copyright 2017 NXP
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/speed.h>
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#include <fsl_immap.h>
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#include <asm/arch/mp.h>
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#include <efi_loader.h>
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#include <fm_eth.h>
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#include <fsl-mc/fsl_mc.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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#include <asm/armv8/sec_firmware.h>
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#ifdef CONFIG_SYS_FSL_DDR
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#include <fsl_ddr.h>
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#endif
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#include <asm/arch/clock.h>
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#include <hwconfig.h>
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#include <fsl_qbman.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct mm_region *mem_map = early_map;
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void cpu_name(char *name)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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unsigned int i, svr, ver;
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svr = gur_in32(&gur->svr);
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ver = SVR_SOC_VER(svr);
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
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strcpy(name, cpu_type_list[i].name);
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if (IS_E_PROCESSOR(svr))
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strcat(name, "E");
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sprintf(name + strlen(name), " Rev%d.%d",
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SVR_MAJ(svr), SVR_MIN(svr));
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break;
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}
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if (i == ARRAY_SIZE(cpu_type_list))
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strcpy(name, "unknown");
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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/*
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* To start MMU before DDR is available, we create MMU table in SRAM.
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* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
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* levels of translation tables here to cover 40-bit address space.
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* We use 4KB granule size, with 40 bits physical address, T0SZ=24
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* Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
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* Note, the debug print in cache_v8.c is not usable for debugging
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* these early MMU tables because UART is not yet available.
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*/
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static inline void early_mmu_setup(void)
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{
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unsigned int el = current_el();
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/* global data is already setup, no allocation yet */
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gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
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gd->arch.tlb_fillptr = gd->arch.tlb_addr;
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gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
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/* Create early page tables */
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setup_pgtables();
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/* point TTBR to the new table */
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set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
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get_tcr(el, NULL, NULL) &
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~(TCR_ORGN_MASK | TCR_IRGN_MASK),
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MEMORY_ATTRIBUTES);
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set_sctlr(get_sctlr() | CR_M);
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}
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static void fix_pcie_mmu_map(void)
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{
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#ifdef CONFIG_ARCH_LS2080A
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unsigned int i;
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u32 svr, ver;
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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svr = gur_in32(&gur->svr);
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ver = SVR_SOC_VER(svr);
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/* Fix PCIE base and size for LS2088A */
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if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
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(ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
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(ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
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for (i = 0; i < ARRAY_SIZE(final_map); i++) {
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switch (final_map[i].phys) {
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case CONFIG_SYS_PCIE1_PHYS_ADDR:
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final_map[i].phys = 0x2000000000ULL;
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final_map[i].virt = 0x2000000000ULL;
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final_map[i].size = 0x800000000ULL;
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break;
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case CONFIG_SYS_PCIE2_PHYS_ADDR:
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final_map[i].phys = 0x2800000000ULL;
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final_map[i].virt = 0x2800000000ULL;
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final_map[i].size = 0x800000000ULL;
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break;
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case CONFIG_SYS_PCIE3_PHYS_ADDR:
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final_map[i].phys = 0x3000000000ULL;
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final_map[i].virt = 0x3000000000ULL;
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final_map[i].size = 0x800000000ULL;
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break;
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case CONFIG_SYS_PCIE4_PHYS_ADDR:
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final_map[i].phys = 0x3800000000ULL;
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final_map[i].virt = 0x3800000000ULL;
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final_map[i].size = 0x800000000ULL;
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break;
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default:
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break;
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}
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}
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}
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#endif
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}
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/*
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* The final tables look similar to early tables, but different in detail.
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* These tables are in DRAM. Sub tables are added to enable cache for
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* QBMan and OCRAM.
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*
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* Put the MMU table in secure memory if gd->arch.secure_ram is valid.
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* OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
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*/
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static inline void final_mmu_setup(void)
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{
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u64 tlb_addr_save = gd->arch.tlb_addr;
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unsigned int el = current_el();
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int index;
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/* fix the final_map before filling in the block entries */
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fix_pcie_mmu_map();
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mem_map = final_map;
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/* Update mapping for DDR to actual size */
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for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
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/*
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* Find the entry for DDR mapping and update the address and
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* size. Zero-sized mapping will be skipped when creating MMU
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* table.
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*/
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switch (final_map[index].virt) {
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case CONFIG_SYS_FSL_DRAM_BASE1:
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final_map[index].virt = gd->bd->bi_dram[0].start;
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final_map[index].phys = gd->bd->bi_dram[0].start;
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final_map[index].size = gd->bd->bi_dram[0].size;
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break;
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#ifdef CONFIG_SYS_FSL_DRAM_BASE2
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case CONFIG_SYS_FSL_DRAM_BASE2:
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#if (CONFIG_NR_DRAM_BANKS >= 2)
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final_map[index].virt = gd->bd->bi_dram[1].start;
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final_map[index].phys = gd->bd->bi_dram[1].start;
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final_map[index].size = gd->bd->bi_dram[1].size;
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#else
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final_map[index].size = 0;
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#endif
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break;
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#endif
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#ifdef CONFIG_SYS_FSL_DRAM_BASE3
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case CONFIG_SYS_FSL_DRAM_BASE3:
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#if (CONFIG_NR_DRAM_BANKS >= 3)
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final_map[index].virt = gd->bd->bi_dram[2].start;
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final_map[index].phys = gd->bd->bi_dram[2].start;
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final_map[index].size = gd->bd->bi_dram[2].size;
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#else
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final_map[index].size = 0;
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#endif
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break;
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#endif
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default:
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break;
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}
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}
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
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if (el == 3) {
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/*
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* Only use gd->arch.secure_ram if the address is
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* recalculated. Align to 4KB for MMU table.
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*/
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/* put page tables in secure ram */
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index = ARRAY_SIZE(final_map) - 2;
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gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
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final_map[index].virt = gd->arch.secure_ram & ~0x3;
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final_map[index].phys = final_map[index].virt;
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final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
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final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
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gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
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tlb_addr_save = gd->arch.tlb_addr;
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} else {
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/* Use allocated (board_f.c) memory for TLB */
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tlb_addr_save = gd->arch.tlb_allocated;
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gd->arch.tlb_addr = tlb_addr_save;
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}
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}
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#endif
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/* Reset the fill ptr */
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gd->arch.tlb_fillptr = tlb_addr_save;
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/* Create normal system page tables */
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setup_pgtables();
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/* Create emergency page tables */
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gd->arch.tlb_addr = gd->arch.tlb_fillptr;
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gd->arch.tlb_emerg = gd->arch.tlb_addr;
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setup_pgtables();
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gd->arch.tlb_addr = tlb_addr_save;
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/* Disable cache and MMU */
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dcache_disable(); /* TLBs are invalidated */
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invalidate_icache_all();
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/* point TTBR to the new table */
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set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
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MEMORY_ATTRIBUTES);
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set_sctlr(get_sctlr() | CR_M);
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}
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u64 get_page_table_size(void)
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{
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return 0x10000;
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}
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int arch_cpu_init(void)
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{
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/*
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* This function is called before U-Boot relocates itself to speed up
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* on system running. It is not necessary to run if performance is not
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* critical. Skip if MMU is already enabled by SPL or other means.
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*/
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if (get_sctlr() & CR_M)
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return 0;
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icache_enable();
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__asm_invalidate_dcache_all();
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__asm_invalidate_tlb_all();
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early_mmu_setup();
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set_sctlr(get_sctlr() | CR_C);
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return 0;
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}
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void mmu_setup(void)
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{
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final_mmu_setup();
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}
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/*
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* This function is called from common/board_r.c.
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* It recreates MMU table in main memory.
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*/
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void enable_caches(void)
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{
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mmu_setup();
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__asm_invalidate_tlb_all();
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icache_enable();
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dcache_enable();
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}
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#endif
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u32 initiator_type(u32 cluster, int init_id)
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{
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
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u32 type = 0;
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type = gur_in32(&gur->tp_ityp[idx]);
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if (type & TP_ITYP_AV)
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return type;
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return 0;
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}
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u32 cpu_pos_mask(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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int i = 0;
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u32 cluster, type, mask = 0;
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do {
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int j;
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cluster = gur_in32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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type = initiator_type(cluster, j);
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if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
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mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
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}
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i++;
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} while ((cluster & TP_CLUSTER_EOC) == 0x0);
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return mask;
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}
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u32 cpu_mask(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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int i = 0, count = 0;
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u32 cluster, type, mask = 0;
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do {
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int j;
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cluster = gur_in32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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type = initiator_type(cluster, j);
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if (type) {
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if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
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mask |= 1 << count;
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count++;
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}
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}
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i++;
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} while ((cluster & TP_CLUSTER_EOC) == 0x0);
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return mask;
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}
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/*
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* Return the number of cores on this SOC.
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*/
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int cpu_numcores(void)
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{
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return hweight32(cpu_mask());
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}
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int fsl_qoriq_core_to_cluster(unsigned int core)
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{
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struct ccsr_gur __iomem *gur =
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(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
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int i = 0, count = 0;
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u32 cluster;
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do {
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int j;
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cluster = gur_in32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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if (initiator_type(cluster, j)) {
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if (count == core)
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return i;
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count++;
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}
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}
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i++;
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} while ((cluster & TP_CLUSTER_EOC) == 0x0);
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return -1; /* cannot identify the cluster */
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}
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u32 fsl_qoriq_core_to_type(unsigned int core)
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{
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struct ccsr_gur __iomem *gur =
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(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
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int i = 0, count = 0;
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u32 cluster, type;
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do {
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int j;
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cluster = gur_in32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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type = initiator_type(cluster, j);
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if (type) {
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if (count == core)
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return type;
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count++;
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}
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}
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i++;
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} while ((cluster & TP_CLUSTER_EOC) == 0x0);
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return -1; /* cannot identify the cluster */
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}
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#ifndef CONFIG_FSL_LSCH3
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uint get_svr(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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return gur_in32(&gur->svr);
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}
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#endif
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#ifdef CONFIG_DISPLAY_CPUINFO
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int print_cpuinfo(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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struct sys_info sysinfo;
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char buf[32];
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unsigned int i, core;
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u32 type, rcw, svr = gur_in32(&gur->svr);
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puts("SoC: ");
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cpu_name(buf);
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printf(" %s (0x%x)\n", buf, svr);
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memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
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get_sys_info(&sysinfo);
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puts("Clock Configuration:");
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for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
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if (!(i % 3))
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puts("\n ");
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type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
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printf("CPU%d(%s):%-4s MHz ", core,
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type == TY_ITYP_VER_A7 ? "A7 " :
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(type == TY_ITYP_VER_A53 ? "A53" :
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(type == TY_ITYP_VER_A57 ? "A57" :
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(type == TY_ITYP_VER_A72 ? "A72" : " "))),
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strmhz(buf, sysinfo.freq_processor[core]));
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}
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/* Display platform clock as Bus frequency. */
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printf("\n Bus: %-4s MHz ",
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strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
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printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
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#ifdef CONFIG_SYS_DPAA_FMAN
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printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
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#endif
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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if (soc_has_dp_ddr()) {
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printf(" DP-DDR: %-4s MT/s",
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strmhz(buf, sysinfo.freq_ddrbus2));
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}
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#endif
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puts("\n");
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/*
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* Display the RCW, so that no one gets confused as to what RCW
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* we're actually using for this boot.
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*/
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puts("Reset Configuration Word (RCW):");
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for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
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rcw = gur_in32(&gur->rcwsr[i]);
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if ((i % 4) == 0)
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printf("\n %08x:", i * 4);
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printf(" %08x", rcw);
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}
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puts("\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_FSL_ESDHC
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int cpu_mmc_init(bd_t *bis)
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{
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return fsl_esdhc_mmc_init(bis);
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}
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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int error = 0;
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#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
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error = fsl_mc_ldpaa_init(bis);
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#endif
|
|
#ifdef CONFIG_FMAN_ENET
|
|
fm_standard_init(bis);
|
|
#endif
|
|
return error;
|
|
}
|
|
|
|
static inline int check_psci(void)
|
|
{
|
|
unsigned int psci_ver;
|
|
|
|
psci_ver = sec_firmware_support_psci_version();
|
|
if (psci_ver == PSCI_INVALID_VER)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void config_core_prefetch(void)
|
|
{
|
|
char *buf = NULL;
|
|
char buffer[HWCONFIG_BUFFER_SIZE];
|
|
const char *prefetch_arg = NULL;
|
|
size_t arglen;
|
|
unsigned int mask;
|
|
struct pt_regs regs;
|
|
|
|
if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
|
|
buf = buffer;
|
|
|
|
prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
|
|
&arglen, buf);
|
|
|
|
if (prefetch_arg) {
|
|
mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
|
|
if (mask & 0x1) {
|
|
printf("Core0 prefetch can't be disabled\n");
|
|
return;
|
|
}
|
|
|
|
#define SIP_PREFETCH_DISABLE_64 0xC200FF13
|
|
regs.regs[0] = SIP_PREFETCH_DISABLE_64;
|
|
regs.regs[1] = mask;
|
|
smc_call(®s);
|
|
|
|
if (regs.regs[0])
|
|
printf("Prefetch disable config failed for mask ");
|
|
else
|
|
printf("Prefetch disable config passed for mask ");
|
|
printf("0x%x\n", mask);
|
|
}
|
|
}
|
|
|
|
int arch_early_init_r(void)
|
|
{
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
|
|
u32 svr_dev_id;
|
|
/*
|
|
* erratum A009635 is valid only for LS2080A SoC and
|
|
* its personalitiesi
|
|
*/
|
|
svr_dev_id = get_svr();
|
|
if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
|
|
erratum_a009635();
|
|
#endif
|
|
#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
|
|
erratum_a009942_check_cpo();
|
|
#endif
|
|
if (check_psci()) {
|
|
debug("PSCI: PSCI does not exist.\n");
|
|
|
|
/* if PSCI does not exist, boot secondary cores here */
|
|
if (fsl_layerscape_wake_seconday_cores())
|
|
printf("Did not wake secondary cores\n");
|
|
}
|
|
|
|
#ifdef CONFIG_SYS_FSL_HAS_RGMII
|
|
fsl_rgmii_init();
|
|
#endif
|
|
|
|
config_core_prefetch();
|
|
|
|
#ifdef CONFIG_SYS_HAS_SERDES
|
|
fsl_serdes_init();
|
|
#endif
|
|
#ifdef CONFIG_FMAN_ENET
|
|
fman_enet_init();
|
|
#endif
|
|
#ifdef CONFIG_SYS_DPAA_QBMAN
|
|
setup_qbman_portals();
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int timer_init(void)
|
|
{
|
|
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
|
|
#ifdef CONFIG_FSL_LSCH3
|
|
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
|
|
#endif
|
|
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
|
|
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
|
|
u32 svr_dev_id;
|
|
#endif
|
|
#ifdef COUNTER_FREQUENCY_REAL
|
|
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
|
|
|
|
/* Update with accurate clock frequency */
|
|
if (current_el() == 3)
|
|
asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_LSCH3
|
|
/* Enable timebase for all clusters.
|
|
* It is safe to do so even some clusters are not enabled.
|
|
*/
|
|
out_le32(cltbenr, 0xf);
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
|
|
/*
|
|
* In certain Layerscape SoCs, the clock for each core's
|
|
* has an enable bit in the PMU Physical Core Time Base Enable
|
|
* Register (PCTBENR), which allows the watchdog to operate.
|
|
*/
|
|
setbits_le32(pctbenr, 0xff);
|
|
/*
|
|
* For LS2080A SoC and its personalities, timer controller
|
|
* offset is different
|
|
*/
|
|
svr_dev_id = get_svr();
|
|
if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
|
|
cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
|
|
|
|
#endif
|
|
|
|
/* Enable clock for timer
|
|
* This is a global setting.
|
|
*/
|
|
out_le32(cntcr, 0x1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
|
|
|
|
void __efi_runtime reset_cpu(ulong addr)
|
|
{
|
|
u32 val;
|
|
|
|
/* Raise RESET_REQ_B */
|
|
val = scfg_in32(rstcr);
|
|
val |= 0x02;
|
|
scfg_out32(rstcr, val);
|
|
}
|
|
|
|
#ifdef CONFIG_EFI_LOADER
|
|
|
|
void __efi_runtime EFIAPI efi_reset_system(
|
|
enum efi_reset_type reset_type,
|
|
efi_status_t reset_status,
|
|
unsigned long data_size, void *reset_data)
|
|
{
|
|
switch (reset_type) {
|
|
case EFI_RESET_COLD:
|
|
case EFI_RESET_WARM:
|
|
case EFI_RESET_PLATFORM_SPECIFIC:
|
|
reset_cpu(0);
|
|
break;
|
|
case EFI_RESET_SHUTDOWN:
|
|
/* Nothing we can do */
|
|
break;
|
|
}
|
|
|
|
while (1) { }
|
|
}
|
|
|
|
efi_status_t efi_reset_system_init(void)
|
|
{
|
|
return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
|
|
}
|
|
|
|
#endif
|
|
|
|
/*
|
|
* Calculate reserved memory with given memory bank
|
|
* Return aligned memory size on success
|
|
* Return (ram_size + needed size) for failure
|
|
*/
|
|
phys_size_t board_reserve_ram_top(phys_size_t ram_size)
|
|
{
|
|
phys_size_t ram_top = ram_size;
|
|
|
|
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
|
|
ram_top = mc_get_dram_block_size();
|
|
if (ram_top > ram_size)
|
|
return ram_size + ram_top;
|
|
|
|
ram_top = ram_size - ram_top;
|
|
/* The start address of MC reserved memory needs to be aligned. */
|
|
ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
|
|
#endif
|
|
|
|
return ram_size - ram_top;
|
|
}
|
|
|
|
phys_size_t get_effective_memsize(void)
|
|
{
|
|
phys_size_t ea_size, rem = 0;
|
|
|
|
/*
|
|
* For ARMv8 SoCs, DDR memory is split into two or three regions. The
|
|
* first region is 2GB space at 0x8000_0000. Secure memory needs to
|
|
* allocated from first region. If the memory extends to the second
|
|
* region (or the third region if applicable), Management Complex (MC)
|
|
* memory should be put into the highest region, i.e. the end of DDR
|
|
* memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
|
|
* U-Boot doesn't relocate itself into higher address. Should DDR be
|
|
* configured to skip the first region, this function needs to be
|
|
* adjusted.
|
|
*/
|
|
if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
|
|
ea_size = CONFIG_MAX_MEM_MAPPED;
|
|
rem = gd->ram_size - ea_size;
|
|
} else {
|
|
ea_size = gd->ram_size;
|
|
}
|
|
|
|
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
|
/* Check if we have enough space for secure memory */
|
|
if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
|
|
ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
|
|
else
|
|
printf("Error: No enough space for secure memory.\n");
|
|
#endif
|
|
/* Check if we have enough memory for MC */
|
|
if (rem < board_reserve_ram_top(rem)) {
|
|
/* Not enough memory in high region to reserve */
|
|
if (ea_size > board_reserve_ram_top(ea_size))
|
|
ea_size -= board_reserve_ram_top(ea_size);
|
|
else
|
|
printf("Error: No enough space for reserved memory.\n");
|
|
}
|
|
|
|
return ea_size;
|
|
}
|
|
|
|
int dram_init_banksize(void)
|
|
{
|
|
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
|
|
phys_size_t dp_ddr_size;
|
|
#endif
|
|
|
|
/*
|
|
* gd->ram_size has the total size of DDR memory, less reserved secure
|
|
* memory. The DDR extends from low region to high region(s) presuming
|
|
* no hole is created with DDR configuration. gd->arch.secure_ram tracks
|
|
* the location of secure memory. gd->arch.resv_ram tracks the location
|
|
* of reserved memory for Management Complex (MC). Because gd->ram_size
|
|
* is reduced by this function if secure memory is reserved, checking
|
|
* gd->arch.secure_ram should be done to avoid running it repeatedly.
|
|
*/
|
|
|
|
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
|
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
|
|
debug("No need to run again, skip %s\n", __func__);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
|
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
|
|
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
|
|
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
|
|
gd->bd->bi_dram[1].size = gd->ram_size -
|
|
CONFIG_SYS_DDR_BLOCK1_SIZE;
|
|
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
|
|
if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
|
|
gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
|
|
gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
|
|
CONFIG_SYS_DDR_BLOCK2_SIZE;
|
|
gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
|
|
}
|
|
#endif
|
|
} else {
|
|
gd->bd->bi_dram[0].size = gd->ram_size;
|
|
}
|
|
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
|
if (gd->bd->bi_dram[0].size >
|
|
CONFIG_SYS_MEM_RESERVE_SECURE) {
|
|
gd->bd->bi_dram[0].size -=
|
|
CONFIG_SYS_MEM_RESERVE_SECURE;
|
|
gd->arch.secure_ram = gd->bd->bi_dram[0].start +
|
|
gd->bd->bi_dram[0].size;
|
|
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
|
|
gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
|
|
}
|
|
#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
|
|
|
|
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
|
|
/* Assign memory for MC */
|
|
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
|
|
if (gd->bd->bi_dram[2].size >=
|
|
board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
|
|
gd->arch.resv_ram = gd->bd->bi_dram[2].start +
|
|
gd->bd->bi_dram[2].size -
|
|
board_reserve_ram_top(gd->bd->bi_dram[2].size);
|
|
} else
|
|
#endif
|
|
{
|
|
if (gd->bd->bi_dram[1].size >=
|
|
board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
|
|
gd->arch.resv_ram = gd->bd->bi_dram[1].start +
|
|
gd->bd->bi_dram[1].size -
|
|
board_reserve_ram_top(gd->bd->bi_dram[1].size);
|
|
} else if (gd->bd->bi_dram[0].size >
|
|
board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
|
|
gd->arch.resv_ram = gd->bd->bi_dram[0].start +
|
|
gd->bd->bi_dram[0].size -
|
|
board_reserve_ram_top(gd->bd->bi_dram[0].size);
|
|
}
|
|
}
|
|
#endif /* CONFIG_FSL_MC_ENET */
|
|
|
|
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
|
|
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
|
|
#error "This SoC shouldn't have DP DDR"
|
|
#endif
|
|
if (soc_has_dp_ddr()) {
|
|
/* initialize DP-DDR here */
|
|
puts("DP-DDR: ");
|
|
/*
|
|
* DDR controller use 0 as the base address for binding.
|
|
* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
|
|
*/
|
|
dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
|
|
CONFIG_DP_DDR_CTRL,
|
|
CONFIG_DP_DDR_NUM_CTRLS,
|
|
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
|
|
NULL, NULL, NULL);
|
|
if (dp_ddr_size) {
|
|
gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
|
|
gd->bd->bi_dram[2].size = dp_ddr_size;
|
|
} else {
|
|
puts("Not detected");
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
|
debug("%s is called. gd->ram_size is reduced to %lu\n",
|
|
__func__, (ulong)gd->ram_size);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
|
|
void efi_add_known_memory(void)
|
|
{
|
|
int i;
|
|
phys_addr_t ram_start, start;
|
|
phys_size_t ram_size;
|
|
u64 pages;
|
|
|
|
/* Add RAM */
|
|
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
|
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
|
|
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
|
|
#error "This SoC shouldn't have DP DDR"
|
|
#endif
|
|
if (i == 2)
|
|
continue; /* skip DP-DDR */
|
|
#endif
|
|
ram_start = gd->bd->bi_dram[i].start;
|
|
ram_size = gd->bd->bi_dram[i].size;
|
|
#ifdef CONFIG_RESV_RAM
|
|
if (gd->arch.resv_ram >= ram_start &&
|
|
gd->arch.resv_ram < ram_start + ram_size)
|
|
ram_size = gd->arch.resv_ram - ram_start;
|
|
#endif
|
|
start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
|
|
pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
|
|
|
|
efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
|
|
false);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Before DDR size is known, early MMU table have DDR mapped as device memory
|
|
* to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
|
|
* needs to be set for these mappings.
|
|
* If a special case configures DDR with holes in the mapping, the holes need
|
|
* to be marked as invalid. This is not implemented in this function.
|
|
*/
|
|
void update_early_mmu_table(void)
|
|
{
|
|
if (!gd->arch.tlb_addr)
|
|
return;
|
|
|
|
if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
|
|
mmu_change_region_attr(
|
|
CONFIG_SYS_SDRAM_BASE,
|
|
gd->ram_size,
|
|
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_OUTER_SHARE |
|
|
PTE_BLOCK_NS |
|
|
PTE_TYPE_VALID);
|
|
} else {
|
|
mmu_change_region_attr(
|
|
CONFIG_SYS_SDRAM_BASE,
|
|
CONFIG_SYS_DDR_BLOCK1_SIZE,
|
|
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_OUTER_SHARE |
|
|
PTE_BLOCK_NS |
|
|
PTE_TYPE_VALID);
|
|
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
|
|
#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
|
|
#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
|
|
#endif
|
|
if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
|
|
CONFIG_SYS_DDR_BLOCK2_SIZE) {
|
|
mmu_change_region_attr(
|
|
CONFIG_SYS_DDR_BLOCK2_BASE,
|
|
CONFIG_SYS_DDR_BLOCK2_SIZE,
|
|
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_OUTER_SHARE |
|
|
PTE_BLOCK_NS |
|
|
PTE_TYPE_VALID);
|
|
mmu_change_region_attr(
|
|
CONFIG_SYS_DDR_BLOCK3_BASE,
|
|
gd->ram_size -
|
|
CONFIG_SYS_DDR_BLOCK1_SIZE -
|
|
CONFIG_SYS_DDR_BLOCK2_SIZE,
|
|
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_OUTER_SHARE |
|
|
PTE_BLOCK_NS |
|
|
PTE_TYPE_VALID);
|
|
} else
|
|
#endif
|
|
{
|
|
mmu_change_region_attr(
|
|
CONFIG_SYS_DDR_BLOCK2_BASE,
|
|
gd->ram_size -
|
|
CONFIG_SYS_DDR_BLOCK1_SIZE,
|
|
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_OUTER_SHARE |
|
|
PTE_BLOCK_NS |
|
|
PTE_TYPE_VALID);
|
|
}
|
|
}
|
|
}
|
|
|
|
__weak int dram_init(void)
|
|
{
|
|
fsl_initdram();
|
|
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
|
|
/* This will break-before-make MMU for DDR */
|
|
update_early_mmu_table();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|