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![Paul Burton](/assets/img/avatar_default.png)
In order to prepare for MIPS arch code making use of arch_cpu_init in a later patch, stop using it from ath79 SoC code & instead use the new mach_cpu_init which is provided for this purpose. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
143 lines
3.6 KiB
C
143 lines
3.6 KiB
C
/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ath79.h>
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#include <mach/ar71xx_regs.h>
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struct ath79_soc_desc {
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const enum ath79_soc_type soc;
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const char *chip;
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const int major;
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const int minor;
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};
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static const struct ath79_soc_desc desc[] = {
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{ATH79_SOC_AR7130, "7130",
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REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7130},
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{ATH79_SOC_AR7141, "7141",
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REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7141},
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{ATH79_SOC_AR7161, "7161",
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REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7161},
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{ATH79_SOC_AR7240, "7240", REV_ID_MAJOR_AR7240, 0},
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{ATH79_SOC_AR7241, "7241", REV_ID_MAJOR_AR7241, 0},
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{ATH79_SOC_AR7242, "7242", REV_ID_MAJOR_AR7242, 0},
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{ATH79_SOC_AR9130, "9130",
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REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9130},
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{ATH79_SOC_AR9132, "9132",
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REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9132},
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{ATH79_SOC_AR9330, "9330", REV_ID_MAJOR_AR9330, 0},
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{ATH79_SOC_AR9331, "9331", REV_ID_MAJOR_AR9331, 0},
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{ATH79_SOC_AR9341, "9341", REV_ID_MAJOR_AR9341, 0},
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{ATH79_SOC_AR9342, "9342", REV_ID_MAJOR_AR9342, 0},
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{ATH79_SOC_AR9344, "9344", REV_ID_MAJOR_AR9344, 0},
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{ATH79_SOC_QCA9533, "9533", REV_ID_MAJOR_QCA9533, 0},
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{ATH79_SOC_QCA9533, "9533",
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REV_ID_MAJOR_QCA9533_V2, 0},
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{ATH79_SOC_QCA9556, "9556", REV_ID_MAJOR_QCA9556, 0},
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{ATH79_SOC_QCA9558, "9558", REV_ID_MAJOR_QCA9558, 0},
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{ATH79_SOC_TP9343, "9343", REV_ID_MAJOR_TP9343, 0},
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{ATH79_SOC_QCA9561, "9561", REV_ID_MAJOR_QCA9561, 0},
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};
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int mach_cpu_init(void)
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{
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void __iomem *base;
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enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
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u32 id, major, minor = 0;
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u32 rev = 0, ver = 1;
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int i;
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base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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id = readl(base + AR71XX_RESET_REG_REV_ID);
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major = id & REV_ID_MAJOR_MASK;
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switch (major) {
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case REV_ID_MAJOR_AR71XX:
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case REV_ID_MAJOR_AR913X:
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minor = id & AR71XX_REV_ID_MINOR_MASK;
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rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
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rev &= AR71XX_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_QCA9533_V2:
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ver = 2;
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/* drop through */
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case REV_ID_MAJOR_AR9341:
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case REV_ID_MAJOR_AR9342:
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case REV_ID_MAJOR_AR9344:
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case REV_ID_MAJOR_QCA9533:
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case REV_ID_MAJOR_QCA9556:
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case REV_ID_MAJOR_QCA9558:
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case REV_ID_MAJOR_TP9343:
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case REV_ID_MAJOR_QCA9561:
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rev = id & AR71XX_REV_ID_REVISION2_MASK;
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break;
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default:
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rev = id & AR71XX_REV_ID_REVISION_MASK;
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break;
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}
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for (i = 0; i < ARRAY_SIZE(desc); i++) {
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if ((desc[i].major == major) &&
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(desc[i].minor == minor)) {
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soc = desc[i].soc;
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break;
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}
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}
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gd->arch.id = id;
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gd->arch.soc = soc;
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gd->arch.rev = rev;
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gd->arch.ver = ver;
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return 0;
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}
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int print_cpuinfo(void)
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{
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enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
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const char *chip = "????";
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u32 id, rev, ver;
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int i;
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for (i = 0; i < ARRAY_SIZE(desc); i++) {
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if (desc[i].soc == gd->arch.soc) {
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chip = desc[i].chip;
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soc = desc[i].soc;
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break;
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}
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}
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id = gd->arch.id;
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rev = gd->arch.rev;
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ver = gd->arch.ver;
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switch (soc) {
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case ATH79_SOC_QCA9533:
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case ATH79_SOC_QCA9556:
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case ATH79_SOC_QCA9558:
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case ATH79_SOC_QCA9561:
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printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip,
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ver, rev);
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break;
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case ATH79_SOC_TP9343:
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printf("Qualcomm Atheros TP%s rev %u\n", chip, rev);
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break;
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case ATH79_SOC_UNKNOWN:
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printf("ATH79: unknown SoC, id:0x%08x", id);
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break;
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default:
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printf("Atheros AR%s rev %u\n", chip, rev);
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}
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return 0;
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}
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