u-boot-brain/arch/arm/dts/imx6ul-opos6ul.dtsi

/*
 * Copyright 2017 Armadeus Systems <support@armadeus.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of
 *     the License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "imx6ul.dtsi"

/ {
	memory {
		reg = <0x80000000 0>; /* will be filled by U-Boot */
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	usdhc3_pwrseq: usdhc3-pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-reset-duration = <1>;
	phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_3v3>;
	status = "okay";

	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			interrupt-parent = <&gpio4>;
			interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
			status = "okay";
		};
	};
};

/* Bluetooth */
&uart8 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart8>;
	uart-has-rtscts;
	status = "okay";
};

/* eMMC */
&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	status = "okay";
};

/* WiFi */
&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	no-1-8-v;
	non-removable;
	mmc-pwrseq = <&usdhc3_pwrseq>;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;

	brcmf: bcrmf@1 {
		compatible = "brcm,bcm4329-fmac";
		reg = <1>;
		interrupt-parent = <&gpio2>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "host-wake";
	};
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x130b0
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x130b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x130b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x130b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			/* INT# */
			MX6UL_PAD_NAND_DQS__GPIO4_IO16		0x1b0b0
			/* RST# */
			MX6UL_PAD_NAND_DATA00__GPIO4_IO02	0x130b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
		>;
	};

	pinctrl_uart8: uart8grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS	0x1b0b0
			/* BT_REG_ON */
			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x130b0
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
			MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
			MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
			MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
			MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA18__USDHC2_CMD	0x1b0b0
			MX6UL_PAD_LCD_DATA19__USDHC2_CLK	0x100b0
			MX6UL_PAD_LCD_DATA20__USDHC2_DATA0	0x1b0b0
			MX6UL_PAD_LCD_DATA21__USDHC2_DATA1	0x1b0b0
			MX6UL_PAD_LCD_DATA22__USDHC2_DATA2	0x1b0b0
			MX6UL_PAD_LCD_DATA23__USDHC2_DATA3	0x1b0b0
			/* WL_REG_ON */
			MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09	0x130b0
			/* WL_IRQ */
			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x1b0b0
		>;
	};
};