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![Mike Frysinger](/assets/img/avatar_default.png)
The driver name does not need to be writable, so constify it. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
654 lines
17 KiB
C
654 lines
17 KiB
C
/*
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* Cirrus Logic EP93xx ethernet MAC / MII driver.
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*
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* Copyright (C) 2010, 2009
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* Matthias Kaehlcke <matthias@kaehlcke.net>
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*
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* Copyright (C) 2004, 2005
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* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
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*
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* Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
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* which is
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*
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* (C) Copyright 2002 2003
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* Adam Bezanson, Network Audio Technologies, Inc.
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* <bezanson@netaudiotech.com>
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*
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* See file CREDITS for list of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <command.h>
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#include <common.h>
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#include <asm/arch/ep93xx.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <linux/types.h>
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#include "ep93xx_eth.h"
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#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv)
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#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
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/* ep93xx_miiphy ops forward declarations */
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static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr,
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unsigned char const reg, unsigned short * const value);
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static int ep93xx_miiphy_write(const char * const dev, unsigned char const addr,
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unsigned char const reg, unsigned short const value);
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#if defined(EP93XX_MAC_DEBUG)
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/**
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* Dump ep93xx_mac values to the terminal.
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*/
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static void dump_dev(struct eth_device *dev)
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{
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struct ep93xx_priv *priv = GET_PRIV(dev);
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int i;
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printf("\ndump_dev()\n");
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printf(" rx_dq.base %p\n", priv->rx_dq.base);
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printf(" rx_dq.current %p\n", priv->rx_dq.current);
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printf(" rx_dq.end %p\n", priv->rx_dq.end);
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printf(" rx_sq.base %p\n", priv->rx_sq.base);
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printf(" rx_sq.current %p\n", priv->rx_sq.current);
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printf(" rx_sq.end %p\n", priv->rx_sq.end);
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for (i = 0; i < NUMRXDESC; i++)
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printf(" rx_buffer[%2.d] %p\n", i, NetRxPackets[i]);
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printf(" tx_dq.base %p\n", priv->tx_dq.base);
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printf(" tx_dq.current %p\n", priv->tx_dq.current);
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printf(" tx_dq.end %p\n", priv->tx_dq.end);
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printf(" tx_sq.base %p\n", priv->tx_sq.base);
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printf(" tx_sq.current %p\n", priv->tx_sq.current);
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printf(" tx_sq.end %p\n", priv->tx_sq.end);
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}
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/**
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* Dump all RX status queue entries to the terminal.
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*/
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static void dump_rx_status_queue(struct eth_device *dev)
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{
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struct ep93xx_priv *priv = GET_PRIV(dev);
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int i;
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printf("\ndump_rx_status_queue()\n");
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printf(" descriptor address word1 word2\n");
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for (i = 0; i < NUMRXDESC; i++) {
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printf(" [ %p ] %08X %08X\n",
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priv->rx_sq.base + i,
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(priv->rx_sq.base + i)->word1,
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(priv->rx_sq.base + i)->word2);
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}
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}
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/**
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* Dump all RX descriptor queue entries to the terminal.
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*/
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static void dump_rx_descriptor_queue(struct eth_device *dev)
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{
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struct ep93xx_priv *priv = GET_PRIV(dev);
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int i;
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printf("\ndump_rx_descriptor_queue()\n");
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printf(" descriptor address word1 word2\n");
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for (i = 0; i < NUMRXDESC; i++) {
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printf(" [ %p ] %08X %08X\n",
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priv->rx_dq.base + i,
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(priv->rx_dq.base + i)->word1,
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(priv->rx_dq.base + i)->word2);
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}
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}
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/**
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* Dump all TX descriptor queue entries to the terminal.
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*/
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static void dump_tx_descriptor_queue(struct eth_device *dev)
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{
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struct ep93xx_priv *priv = GET_PRIV(dev);
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int i;
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printf("\ndump_tx_descriptor_queue()\n");
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printf(" descriptor address word1 word2\n");
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for (i = 0; i < NUMTXDESC; i++) {
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printf(" [ %p ] %08X %08X\n",
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priv->tx_dq.base + i,
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(priv->tx_dq.base + i)->word1,
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(priv->tx_dq.base + i)->word2);
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}
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}
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/**
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* Dump all TX status queue entries to the terminal.
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*/
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static void dump_tx_status_queue(struct eth_device *dev)
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{
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struct ep93xx_priv *priv = GET_PRIV(dev);
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int i;
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printf("\ndump_tx_status_queue()\n");
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printf(" descriptor address word1\n");
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for (i = 0; i < NUMTXDESC; i++) {
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printf(" [ %p ] %08X\n",
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priv->rx_sq.base + i,
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(priv->rx_sq.base + i)->word1);
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}
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}
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#else
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#define dump_dev(x)
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#define dump_rx_descriptor_queue(x)
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#define dump_rx_status_queue(x)
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#define dump_tx_descriptor_queue(x)
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#define dump_tx_status_queue(x)
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#endif /* defined(EP93XX_MAC_DEBUG) */
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/**
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* Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
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* it's cleared.
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*/
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static void ep93xx_mac_reset(struct eth_device *dev)
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{
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struct mac_regs *mac = GET_REGS(dev);
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uint32_t value;
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debug("+ep93xx_mac_reset");
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value = readl(&mac->selfctl);
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value |= SELFCTL_RESET;
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writel(value, &mac->selfctl);
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while (readl(&mac->selfctl) & SELFCTL_RESET)
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; /* noop */
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debug("-ep93xx_mac_reset");
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}
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/* Eth device open */
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static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd)
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{
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struct ep93xx_priv *priv = GET_PRIV(dev);
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struct mac_regs *mac = GET_REGS(dev);
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uchar *mac_addr = dev->enetaddr;
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int i;
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debug("+ep93xx_eth_open");
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/* Reset the MAC */
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ep93xx_mac_reset(dev);
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/* Reset the descriptor queues' current and end address values */
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priv->tx_dq.current = priv->tx_dq.base;
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priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
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priv->tx_sq.current = priv->tx_sq.base;
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priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
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priv->rx_dq.current = priv->rx_dq.base;
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priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
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priv->rx_sq.current = priv->rx_sq.base;
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priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
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/*
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* Set the transmit descriptor and status queues' base address,
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* current address, and length registers. Set the maximum frame
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* length and threshold. Enable the transmit descriptor processor.
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*/
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writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);
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writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);
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writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);
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writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);
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writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);
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writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);
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writel(0x00040000, &mac->txdthrshld);
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writel(0x00040000, &mac->txststhrshld);
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writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);
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writel(BMCTL_TXEN, &mac->bmctl);
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/*
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* Set the receive descriptor and status queues' base address,
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* current address, and length registers. Enable the receive
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* descriptor processor.
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*/
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writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);
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writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);
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writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);
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writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);
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writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);
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writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);
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writel(0x00040000, &mac->rxdthrshld);
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writel(BMCTL_RXEN, &mac->bmctl);
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writel(0x00040000, &mac->rxststhrshld);
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/* Wait until the receive descriptor processor is active */
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while (!(readl(&mac->bmsts) & BMSTS_RXACT))
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; /* noop */
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/*
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* Initialize the RX descriptor queue. Clear the TX descriptor queue.
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* Clear the RX and TX status queues. Enqueue the RX descriptor and
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* status entries to the MAC.
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*/
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for (i = 0; i < NUMRXDESC; i++) {
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/* set buffer address */
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(priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i];
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/* set buffer length, clear buffer index and NSOF */
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(priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
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}
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memset(priv->tx_dq.base, 0,
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(sizeof(struct tx_descriptor) * NUMTXDESC));
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memset(priv->rx_sq.base, 0,
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(sizeof(struct rx_status) * NUMRXDESC));
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memset(priv->tx_sq.base, 0,
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(sizeof(struct tx_status) * NUMTXDESC));
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writel(NUMRXDESC, &mac->rxdqenq);
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writel(NUMRXDESC, &mac->rxstsqenq);
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/* Set the primary MAC address */
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writel(AFP_IAPRIMARY, &mac->afp);
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writel(mac_addr[0] | (mac_addr[1] << 8) |
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(mac_addr[2] << 16) | (mac_addr[3] << 24),
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&mac->indad);
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writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);
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/* Turn on RX and TX */
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writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
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RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);
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writel(TXCTL_STXON, &mac->txctl);
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/* Dump data structures if we're debugging */
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dump_dev(dev);
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dump_rx_descriptor_queue(dev);
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dump_rx_status_queue(dev);
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dump_tx_descriptor_queue(dev);
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dump_tx_status_queue(dev);
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debug("-ep93xx_eth_open");
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return 1;
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}
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/**
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* Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
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* registers.
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*/
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static void ep93xx_eth_close(struct eth_device *dev)
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{
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struct mac_regs *mac = GET_REGS(dev);
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debug("+ep93xx_eth_close");
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writel(0x00000000, &mac->rxctl);
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writel(0x00000000, &mac->txctl);
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debug("-ep93xx_eth_close");
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}
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/**
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* Copy a frame of data from the MAC into the protocol layer for further
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* processing.
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*/
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static int ep93xx_eth_rcv_packet(struct eth_device *dev)
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{
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struct mac_regs *mac = GET_REGS(dev);
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struct ep93xx_priv *priv = GET_PRIV(dev);
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int len = -1;
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debug("+ep93xx_eth_rcv_packet");
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if (RX_STATUS_RFP(priv->rx_sq.current)) {
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if (RX_STATUS_RWE(priv->rx_sq.current)) {
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/*
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* We have a good frame. Extract the frame's length
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* from the current rx_status_queue entry, and copy
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* the frame's data into NetRxPackets[] of the
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* protocol stack. We track the total number of
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* bytes in the frame (nbytes_frame) which will be
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* used when we pass the data off to the protocol
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* layer via NetReceive().
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*/
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len = RX_STATUS_FRAME_LEN(priv->rx_sq.current);
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NetReceive((uchar *)priv->rx_dq.current->word1, len);
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debug("reporting %d bytes...\n", len);
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} else {
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/* Do we have an erroneous packet? */
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error("packet rx error, status %08X %08X",
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priv->rx_sq.current->word1,
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priv->rx_sq.current->word2);
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dump_rx_descriptor_queue(dev);
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dump_rx_status_queue(dev);
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}
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/*
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* Clear the associated status queue entry, and
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* increment our current pointers to the next RX
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* descriptor and status queue entries (making sure
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* we wrap properly).
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*/
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memset((void *)priv->rx_sq.current, 0,
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sizeof(struct rx_status));
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priv->rx_sq.current++;
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if (priv->rx_sq.current >= priv->rx_sq.end)
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priv->rx_sq.current = priv->rx_sq.base;
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priv->rx_dq.current++;
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if (priv->rx_dq.current >= priv->rx_dq.end)
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priv->rx_dq.current = priv->rx_dq.base;
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/*
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* Finally, return the RX descriptor and status entries
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* back to the MAC engine, and loop again, checking for
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* more descriptors to process.
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*/
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writel(1, &mac->rxdqenq);
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writel(1, &mac->rxstsqenq);
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} else {
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len = 0;
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}
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debug("-ep93xx_eth_rcv_packet %d", len);
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return len;
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}
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/**
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* Send a block of data via ethernet.
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*/
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static int ep93xx_eth_send_packet(struct eth_device *dev,
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volatile void * const packet, int const length)
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{
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struct mac_regs *mac = GET_REGS(dev);
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struct ep93xx_priv *priv = GET_PRIV(dev);
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int ret = -1;
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debug("+ep93xx_eth_send_packet");
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/* Parameter check */
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BUG_ON(packet == NULL);
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/*
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* Initialize the TX descriptor queue with the new packet's info.
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* Clear the associated status queue entry. Enqueue the packet
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* to the MAC for transmission.
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*/
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/* set buffer address */
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priv->tx_dq.current->word1 = (uint32_t)packet;
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/* set buffer length and EOF bit */
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priv->tx_dq.current->word2 = length | TX_DESC_EOF;
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/* clear tx status */
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priv->tx_sq.current->word1 = 0;
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/* enqueue the TX descriptor */
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writel(1, &mac->txdqenq);
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/* wait for the frame to become processed */
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while (!TX_STATUS_TXFP(priv->tx_sq.current))
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; /* noop */
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if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
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error("packet tx error, status %08X",
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priv->tx_sq.current->word1);
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dump_tx_descriptor_queue(dev);
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dump_tx_status_queue(dev);
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/* TODO: Add better error handling? */
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goto eth_send_out;
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}
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ret = 0;
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/* Fall through */
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eth_send_out:
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debug("-ep93xx_eth_send_packet %d", ret);
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return ret;
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}
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#if defined(CONFIG_MII)
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int ep93xx_miiphy_initialize(bd_t * const bd)
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{
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miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write);
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return 0;
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}
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#endif
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/**
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* Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
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* allocated, if necessary, for the TX and RX descriptor and status queues,
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* as well as for received packets. The EP93XX MAC hardware is initialized.
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* Transmit and receive operations are enabled.
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*/
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int ep93xx_eth_initialize(u8 dev_num, int base_addr)
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{
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int ret = -1;
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struct eth_device *dev;
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struct ep93xx_priv *priv;
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debug("+ep93xx_eth_initialize");
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priv = malloc(sizeof(*priv));
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if (!priv) {
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error("malloc() failed");
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goto eth_init_failed_0;
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}
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memset(priv, 0, sizeof(*priv));
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priv->regs = (struct mac_regs *)base_addr;
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priv->tx_dq.base = calloc(NUMTXDESC,
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sizeof(struct tx_descriptor));
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if (priv->tx_dq.base == NULL) {
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error("calloc() failed");
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goto eth_init_failed_1;
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}
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priv->tx_sq.base = calloc(NUMTXDESC,
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sizeof(struct tx_status));
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if (priv->tx_sq.base == NULL) {
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error("calloc() failed");
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goto eth_init_failed_2;
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}
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priv->rx_dq.base = calloc(NUMRXDESC,
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sizeof(struct rx_descriptor));
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if (priv->rx_dq.base == NULL) {
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error("calloc() failed");
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goto eth_init_failed_3;
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}
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priv->rx_sq.base = calloc(NUMRXDESC,
|
|
sizeof(struct rx_status));
|
|
if (priv->rx_sq.base == NULL) {
|
|
error("calloc() failed");
|
|
goto eth_init_failed_4;
|
|
}
|
|
|
|
dev = malloc(sizeof *dev);
|
|
if (dev == NULL) {
|
|
error("malloc() failed");
|
|
goto eth_init_failed_5;
|
|
}
|
|
memset(dev, 0, sizeof *dev);
|
|
|
|
dev->iobase = base_addr;
|
|
dev->priv = priv;
|
|
dev->init = ep93xx_eth_open;
|
|
dev->halt = ep93xx_eth_close;
|
|
dev->send = ep93xx_eth_send_packet;
|
|
dev->recv = ep93xx_eth_rcv_packet;
|
|
|
|
sprintf(dev->name, "ep93xx_eth-%hu", dev_num);
|
|
|
|
eth_register(dev);
|
|
|
|
/* Done! */
|
|
ret = 1;
|
|
goto eth_init_done;
|
|
|
|
eth_init_failed_5:
|
|
free(priv->rx_sq.base);
|
|
/* Fall through */
|
|
|
|
eth_init_failed_4:
|
|
free(priv->rx_dq.base);
|
|
/* Fall through */
|
|
|
|
eth_init_failed_3:
|
|
free(priv->tx_sq.base);
|
|
/* Fall through */
|
|
|
|
eth_init_failed_2:
|
|
free(priv->tx_dq.base);
|
|
/* Fall through */
|
|
|
|
eth_init_failed_1:
|
|
free(priv);
|
|
/* Fall through */
|
|
|
|
eth_init_failed_0:
|
|
/* Fall through */
|
|
|
|
eth_init_done:
|
|
debug("-ep93xx_eth_initialize %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
#if defined(CONFIG_MII)
|
|
|
|
/**
|
|
* Maximum MII address we support
|
|
*/
|
|
#define MII_ADDRESS_MAX 31
|
|
|
|
/**
|
|
* Maximum MII register address we support
|
|
*/
|
|
#define MII_REGISTER_MAX 31
|
|
|
|
/**
|
|
* Read a 16-bit value from an MII register.
|
|
*/
|
|
static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr,
|
|
unsigned char const reg, unsigned short * const value)
|
|
{
|
|
struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
|
|
int ret = -1;
|
|
uint32_t self_ctl;
|
|
|
|
debug("+ep93xx_miiphy_read");
|
|
|
|
/* Parameter checks */
|
|
BUG_ON(dev == NULL);
|
|
BUG_ON(addr > MII_ADDRESS_MAX);
|
|
BUG_ON(reg > MII_REGISTER_MAX);
|
|
BUG_ON(value == NULL);
|
|
|
|
/*
|
|
* Save the current SelfCTL register value. Set MAC to suppress
|
|
* preamble bits. Wait for any previous MII command to complete
|
|
* before issuing the new command.
|
|
*/
|
|
self_ctl = readl(&mac->selfctl);
|
|
#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
|
|
writel(self_ctl & ~(1 << 8), &mac->selfctl);
|
|
#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
|
|
|
|
while (readl(&mac->miists) & MIISTS_BUSY)
|
|
; /* noop */
|
|
|
|
/*
|
|
* Issue the MII 'read' command. Wait for the command to complete.
|
|
* Read the MII data value.
|
|
*/
|
|
writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg,
|
|
&mac->miicmd);
|
|
while (readl(&mac->miists) & MIISTS_BUSY)
|
|
; /* noop */
|
|
|
|
*value = (unsigned short)readl(&mac->miidata);
|
|
|
|
/* Restore the saved SelfCTL value and return. */
|
|
writel(self_ctl, &mac->selfctl);
|
|
|
|
ret = 0;
|
|
/* Fall through */
|
|
|
|
debug("-ep93xx_miiphy_read");
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* Write a 16-bit value to an MII register.
|
|
*/
|
|
static int ep93xx_miiphy_write(const char * const dev, unsigned char const addr,
|
|
unsigned char const reg, unsigned short const value)
|
|
{
|
|
struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
|
|
int ret = -1;
|
|
uint32_t self_ctl;
|
|
|
|
debug("+ep93xx_miiphy_write");
|
|
|
|
/* Parameter checks */
|
|
BUG_ON(dev == NULL);
|
|
BUG_ON(addr > MII_ADDRESS_MAX);
|
|
BUG_ON(reg > MII_REGISTER_MAX);
|
|
|
|
/*
|
|
* Save the current SelfCTL register value. Set MAC to suppress
|
|
* preamble bits. Wait for any previous MII command to complete
|
|
* before issuing the new command.
|
|
*/
|
|
self_ctl = readl(&mac->selfctl);
|
|
#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
|
|
writel(self_ctl & ~(1 << 8), &mac->selfctl);
|
|
#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
|
|
|
|
while (readl(&mac->miists) & MIISTS_BUSY)
|
|
; /* noop */
|
|
|
|
/* Issue the MII 'write' command. Wait for the command to complete. */
|
|
writel((uint32_t)value, &mac->miidata);
|
|
writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg,
|
|
&mac->miicmd);
|
|
while (readl(&mac->miists) & MIISTS_BUSY)
|
|
; /* noop */
|
|
|
|
/* Restore the saved SelfCTL value and return. */
|
|
writel(self_ctl, &mac->selfctl);
|
|
|
|
ret = 0;
|
|
/* Fall through */
|
|
|
|
debug("-ep93xx_miiphy_write");
|
|
return ret;
|
|
}
|
|
#endif /* defined(CONFIG_MII) */
|