mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 02:49:44 +09:00
43a5f0df2f
This patch adds support for A320 evaluation board from Faraday. This board uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM. FA526 is an ARMv4 processor and uses the ARM920T source in this patch. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
80 lines
2.4 KiB
C
80 lines
2.4 KiB
C
/*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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* Static Memory Controller
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*/
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#ifndef __FTSMC020_H
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#define __FTSMC020_H
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#ifndef __ASSEMBLY__
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struct ftsmc020 {
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struct {
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unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */
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unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */
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} bank[4];
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unsigned int pad[8]; /* 0x20 - 0x3c */
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unsigned int ssr; /* 0x40 */
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};
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void ftsmc020_init(void);
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#endif /* __ASSEMBLY__ */
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/*
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* Memory Bank Configuration Register
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*/
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#define FTSMC020_BANK_ENABLE (1 << 28)
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#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000)
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#define FTSMC020_BANK_WPROT (1 << 11)
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#define FTSMC020_BANK_SIZE_32K (0xb << 4)
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#define FTSMC020_BANK_SIZE_64K (0xc << 4)
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#define FTSMC020_BANK_SIZE_128K (0xd << 4)
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#define FTSMC020_BANK_SIZE_256K (0xe << 4)
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#define FTSMC020_BANK_SIZE_512K (0xf << 4)
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#define FTSMC020_BANK_SIZE_1M (0x0 << 4)
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#define FTSMC020_BANK_SIZE_2M (0x1 << 4)
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#define FTSMC020_BANK_SIZE_4M (0x2 << 4)
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#define FTSMC020_BANK_SIZE_8M (0x3 << 4)
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#define FTSMC020_BANK_SIZE_16M (0x4 << 4)
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#define FTSMC020_BANK_SIZE_32M (0x5 << 4)
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#define FTSMC020_BANK_MBW_8 (0x0 << 0)
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#define FTSMC020_BANK_MBW_16 (0x1 << 0)
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#define FTSMC020_BANK_MBW_32 (0x2 << 0)
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/*
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* Memory Bank Timing Parameter Register
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*/
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#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28)
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#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24)
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#define FTSMC020_TPR_RBE (1 << 20)
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#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18)
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#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16)
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#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12)
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#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8)
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#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6)
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#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4)
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#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0)
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#endif /* __FTSMC020_H */
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