mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
526aabec24
When U-Boot is not the first-stage bootloader the interrupt and cache init must be skipped, as well as init for various peripherals. Update the code to add checks for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
39 lines
708 B
C
39 lines
708 B
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2011
|
|
* Graeme Russ, <graeme.russ@gmail.com>
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <init.h>
|
|
#include <linux/errno.h>
|
|
#include <asm/mtrr.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int init_cache_f_r(void)
|
|
{
|
|
bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) ||
|
|
IS_ENABLED(CONFIG_FSP_VERSION2);
|
|
int ret;
|
|
|
|
do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
|
|
!IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
|
|
|
|
if (do_mtrr) {
|
|
ret = mtrr_commit(false);
|
|
/*
|
|
* If MTRR MSR is not implemented by the processor, just ignore
|
|
* it
|
|
*/
|
|
if (ret && ret != -ENOSYS)
|
|
return ret;
|
|
}
|
|
|
|
if (!ll_boot_init())
|
|
return 0;
|
|
|
|
/* Initialise the CPU cache(s) */
|
|
return init_cache();
|
|
}
|