mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-17 02:03:21 +09:00
3dd22a37aa
This patch makes the necessary changes for making use of I2S0 channel instead of I2S1 channel on smdk board. This changes are done to maintain the uniformity to use I2S0 channel. Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
236 lines
7.1 KiB
C
236 lines
7.1 KiB
C
/*
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* (C) Copyright 2010 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _EXYNOS4_CPU_H
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#define _EXYNOS4_CPU_H
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#define DEVICE_NOT_AVAILABLE 0
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#define EXYNOS_CPU_NAME "Exynos"
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#define EXYNOS4_ADDR_BASE 0x10000000
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/* EXYNOS4 Common*/
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#define EXYNOS4_I2C_SPACING 0x10000
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#define EXYNOS4_GPIO_PART3_BASE 0x03860000
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#define EXYNOS4_PRO_ID 0x10000000
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#define EXYNOS4_SYSREG_BASE 0x10010000
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#define EXYNOS4_POWER_BASE 0x10020000
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#define EXYNOS4_SWRESET 0x10020400
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#define EXYNOS4_CLOCK_BASE 0x10030000
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#define EXYNOS4_SYSTIMER_BASE 0x10050000
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#define EXYNOS4_WATCHDOG_BASE 0x10060000
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#define EXYNOS4_TZPC_BASE 0x10110000
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#define EXYNOS4_MIU_BASE 0x10600000
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#define EXYNOS4_DMC_CTRL_BASE 0x10400000
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#define EXYNOS4_GPIO_PART2_BASE 0x11000000
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#define EXYNOS4_GPIO_PART1_BASE 0x11400000
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#define EXYNOS4_FIMD_BASE 0x11C00000
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#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
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#define EXYNOS4_USBOTG_BASE 0x12480000
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#define EXYNOS4_MMC_BASE 0x12510000
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#define EXYNOS4_SROMC_BASE 0x12570000
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#define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000
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#define EXYNOS4_USBPHY_BASE 0x125B0000
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#define EXYNOS4_UART_BASE 0x13800000
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#define EXYNOS4_I2C_BASE 0x13860000
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#define EXYNOS4_ADC_BASE 0x13910000
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#define EXYNOS4_SPI_BASE 0x13920000
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#define EXYNOS4_PWMTIMER_BASE 0x139D0000
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#define EXYNOS4_MODEM_BASE 0x13A00000
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#define EXYNOS4_USBPHY_CONTROL 0x10020704
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#define EXYNOS4_I2S_BASE 0xE2100000
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#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
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/* EXYNOS4X12 */
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#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
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#define EXYNOS4X12_PRO_ID 0x10000000
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#define EXYNOS4X12_SYSREG_BASE 0x10010000
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#define EXYNOS4X12_POWER_BASE 0x10020000
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#define EXYNOS4X12_SWRESET 0x10020400
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#define EXYNOS4X12_USBPHY_CONTROL 0x10020704
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#define EXYNOS4X12_CLOCK_BASE 0x10030000
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#define EXYNOS4X12_SYSTIMER_BASE 0x10050000
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#define EXYNOS4X12_WATCHDOG_BASE 0x10060000
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#define EXYNOS4X12_TZPC_BASE 0x10110000
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#define EXYNOS4X12_DMC_CTRL_BASE 0x10600000
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#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
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#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
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#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
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#define EXYNOS4X12_FIMD_BASE 0x11C00000
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#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
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#define EXYNOS4X12_USBOTG_BASE 0x12480000
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#define EXYNOS4X12_MMC_BASE 0x12510000
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#define EXYNOS4X12_SROMC_BASE 0x12570000
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#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000
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#define EXYNOS4X12_USBPHY_BASE 0x125B0000
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#define EXYNOS4X12_UART_BASE 0x13800000
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#define EXYNOS4X12_I2C_BASE 0x13860000
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#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000
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#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
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/* EXYNOS5 Common*/
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#define EXYNOS5_I2C_SPACING 0x10000
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#define EXYNOS5_AUDIOSS_BASE 0x03810000
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#define EXYNOS5_GPIO_PART4_BASE 0x03860000
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#define EXYNOS5_PRO_ID 0x10000000
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#define EXYNOS5_CLOCK_BASE 0x10010000
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#define EXYNOS5_POWER_BASE 0x10040000
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#define EXYNOS5_SWRESET 0x10040400
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#define EXYNOS5_SYSREG_BASE 0x10050000
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#define EXYNOS5_TZPC_BASE 0x10100000
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#define EXYNOS5_WATCHDOG_BASE 0x101D0000
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#define EXYNOS5_ACE_SFR_BASE 0x10830000
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#define EXYNOS5_DMC_PHY_BASE 0x10C00000
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#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
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#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
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#define EXYNOS5_GPIO_PART1_BASE 0x11400000
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#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
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#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
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#define EXYNOS5_USBPHY_BASE 0x12130000
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#define EXYNOS5_USBOTG_BASE 0x12140000
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#define EXYNOS5_MMC_BASE 0x12200000
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#define EXYNOS5_SROMC_BASE 0x12250000
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#define EXYNOS5_UART_BASE 0x12C00000
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#define EXYNOS5_I2C_BASE 0x12C60000
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#define EXYNOS5_SPI_BASE 0x12D20000
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#define EXYNOS5_I2S_BASE 0x12D60000
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#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
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#define EXYNOS5_SPI_ISP_BASE 0x131A0000
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#define EXYNOS5_GPIO_PART2_BASE 0x13400000
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#define EXYNOS5_FIMD_BASE 0x14400000
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#define EXYNOS5_DP_BASE 0x145B0000
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#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
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#ifndef __ASSEMBLY__
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#include <asm/io.h>
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/* CPU detection macros */
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extern unsigned int s5p_cpu_id;
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extern unsigned int s5p_cpu_rev;
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static inline int s5p_get_cpu_rev(void)
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{
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return s5p_cpu_rev;
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}
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static inline void s5p_set_cpu_id(void)
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{
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unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
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switch (pro_id) {
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case 0x200:
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/* Exynos4210 EVT0 */
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s5p_cpu_id = 0x4210;
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s5p_cpu_rev = 0;
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break;
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case 0x210:
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/* Exynos4210 EVT1 */
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s5p_cpu_id = 0x4210;
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break;
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case 0x412:
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/* Exynos4412 */
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s5p_cpu_id = 0x4412;
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break;
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case 0x520:
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/* Exynos5250 */
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s5p_cpu_id = 0x5250;
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break;
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}
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}
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static inline char *s5p_get_cpu_name(void)
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{
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return EXYNOS_CPU_NAME;
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}
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#define IS_SAMSUNG_TYPE(type, id) \
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static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \
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{ \
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return (s5p_cpu_id >> 12) == id; \
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}
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IS_SAMSUNG_TYPE(exynos4, 0x4)
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IS_SAMSUNG_TYPE(exynos5, 0x5)
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#define IS_EXYNOS_TYPE(type, id) \
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static inline int __attribute__((no_instrument_function)) \
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proid_is_##type(void) \
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{ \
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return s5p_cpu_id == id; \
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}
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IS_EXYNOS_TYPE(exynos4210, 0x4210)
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IS_EXYNOS_TYPE(exynos4412, 0x4412)
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IS_EXYNOS_TYPE(exynos5250, 0x5250)
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#define SAMSUNG_BASE(device, base) \
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static inline unsigned int __attribute__((no_instrument_function)) \
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samsung_get_base_##device(void) \
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{ \
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if (cpu_is_exynos4()) { \
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if (proid_is_exynos4412()) \
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return EXYNOS4X12_##base; \
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return EXYNOS4_##base; \
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} else if (cpu_is_exynos5()) { \
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return EXYNOS5_##base; \
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} \
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return 0; \
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}
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SAMSUNG_BASE(adc, ADC_BASE)
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SAMSUNG_BASE(clock, CLOCK_BASE)
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SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
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SAMSUNG_BASE(dp, DP_BASE)
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SAMSUNG_BASE(sysreg, SYSREG_BASE)
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SAMSUNG_BASE(fimd, FIMD_BASE)
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SAMSUNG_BASE(i2c, I2C_BASE)
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SAMSUNG_BASE(i2s, I2S_BASE)
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SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
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SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
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SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
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SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
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SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
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SAMSUNG_BASE(pro_id, PRO_ID)
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SAMSUNG_BASE(mmc, MMC_BASE)
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SAMSUNG_BASE(modem, MODEM_BASE)
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SAMSUNG_BASE(sromc, SROMC_BASE)
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SAMSUNG_BASE(swreset, SWRESET)
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SAMSUNG_BASE(timer, PWMTIMER_BASE)
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SAMSUNG_BASE(uart, UART_BASE)
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SAMSUNG_BASE(usb_phy, USBPHY_BASE)
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SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
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SAMSUNG_BASE(usb_otg, USBOTG_BASE)
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SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
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SAMSUNG_BASE(power, POWER_BASE)
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SAMSUNG_BASE(spi, SPI_BASE)
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SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
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SAMSUNG_BASE(tzpc, TZPC_BASE)
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SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
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SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
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SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
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#endif
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#endif /* _EXYNOS4_CPU_H */
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