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https://github.com/brain-hackers/u-boot-brain
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![kevin.morfitt@fearnside-systems.co.uk](/assets/img/avatar_default.png)
This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
362 lines
7.5 KiB
C
362 lines
7.5 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/arch/s3c24x0_cpu.h>
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#include <stdio_dev.h>
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#include <i2c.h>
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#include "vcma9.h"
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#include "../common/common_util.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define FCLK_SPEED 1
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#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
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#define M_MDIV 0xC3
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#define M_PDIV 0x4
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#define M_SDIV 0x1
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#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
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#define M_MDIV 0xA1
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#define M_PDIV 0x3
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#define M_SDIV 0x1
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#endif
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#define USB_CLOCK 1
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#if USB_CLOCK==0
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#define U_M_MDIV 0xA1
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x1
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#elif USB_CLOCK==1
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#define U_M_MDIV 0x48
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x2
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#endif
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static inline void delay(unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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struct s3c24x0_clock_power * const clk_power =
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s3c24x0_get_base_clock_power();
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struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
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/* to reduce PLL lock time, adjust the LOCKTIME register */
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clk_power->LOCKTIME = 0xFFFFFF;
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/* configure MPLL */
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clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
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/* some delay between MPLL and UPLL */
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delay (4000);
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/* configure UPLL */
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clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
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/* some delay between MPLL and UPLL */
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delay (8000);
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/* set up the I/O ports */
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gpio->GPACON = 0x007FFFFF;
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gpio->GPBCON = 0x002AAAAA;
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gpio->GPBUP = 0x000002BF;
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gpio->GPCCON = 0xAAAAAAAA;
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gpio->GPCUP = 0x0000FFFF;
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gpio->GPDCON = 0xAAAAAAAA;
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gpio->GPDUP = 0x0000FFFF;
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gpio->GPECON = 0xAAAAAAAA;
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gpio->GPEUP = 0x000037F7;
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gpio->GPFCON = 0x00000000;
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gpio->GPFUP = 0x00000000;
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gpio->GPGCON = 0xFFEAFF5A;
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gpio->GPGUP = 0x0000F0DC;
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gpio->GPHCON = 0x0028AAAA;
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gpio->GPHUP = 0x00000656;
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/* setup correct IRQ modes for NIC */
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gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
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/* select USB port 2 to be host or device (fix to host for now) */
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gpio->MISCCR |= 0x08;
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/* init serial */
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gd->baudrate = CONFIG_BAUDRATE;
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gd->have_console = 1;
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serial_init();
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/* arch number of VCMA9-Board */
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gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x30000100;
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icache_enable();
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dcache_enable();
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return 0;
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}
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/*
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* NAND flash initialization.
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*/
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#if defined(CONFIG_CMD_NAND)
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extern ulong
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nand_probe(ulong physadr);
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static inline void NF_Reset(void)
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{
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int i;
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NF_SetCE(NFCE_LOW);
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NF_Cmd(0xFF); /* reset command */
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for(i = 0; i < 10; i++); /* tWB = 100ns. */
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NF_WaitRB(); /* wait 200~500us; */
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NF_SetCE(NFCE_HIGH);
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}
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static inline void NF_Init(void)
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{
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#if 0 /* a little bit too optimistic */
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#define TACLS 0
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#define TWRPH0 3
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#define TWRPH1 0
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#else
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#define TACLS 0
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#define TWRPH0 4
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#define TWRPH1 2
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#endif
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NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
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/*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
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/* 1 1 1 1, 1 xxx, r xxx, r xxx */
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/* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
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NF_Reset();
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}
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void
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nand_init(void)
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{
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struct s3c2410_nand * const nand = s3c2410_get_base_nand();
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NF_Init();
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#ifdef DEBUG
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printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
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#endif
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printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
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}
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#endif
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/*
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* Get some Board/PLD Info
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*/
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static u8 Get_PLD_ID(void)
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{
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VCMA9_PLD * const pld = VCMA9_get_base_PLD();
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return(pld->ID);
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}
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static u8 Get_PLD_BOARD(void)
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{
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VCMA9_PLD * const pld = VCMA9_get_base_PLD();
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return(pld->BOARD);
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}
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static u8 Get_PLD_SDRAM(void)
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{
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VCMA9_PLD * const pld = VCMA9_get_base_PLD();
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return(pld->SDRAM);
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}
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static u8 Get_PLD_Version(void)
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{
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return((Get_PLD_ID() >> 4) & 0x0F);
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}
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static u8 Get_PLD_Revision(void)
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{
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return(Get_PLD_ID() & 0x0F);
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}
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#if 0 /* not used */
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static int Get_Board_Config(void)
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{
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u8 config = Get_PLD_BOARD() & 0x03;
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if (config == 3)
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return 1;
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else
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return 0;
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}
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#endif
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static uchar Get_Board_PCB(void)
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{
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return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
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}
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static u8 Get_SDRAM_ChipNr(void)
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{
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switch ((Get_PLD_SDRAM() >> 4) & 0x0F) {
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case 0: return 4;
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case 1: return 1;
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case 2: return 2;
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default: return 0;
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}
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}
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static ulong Get_SDRAM_ChipSize(void)
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{
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switch (Get_PLD_SDRAM() & 0x0F) {
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case 0: return 16 * (1024*1024);
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case 1: return 32 * (1024*1024);
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case 2: return 8 * (1024*1024);
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case 3: return 8 * (1024*1024);
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default: return 0;
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}
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}
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static const char * Get_SDRAM_ChipGeom(void)
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{
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switch (Get_PLD_SDRAM() & 0x0F) {
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case 0: return "4Mx8x4";
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case 1: return "8Mx8x4";
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case 2: return "2Mx8x4";
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case 3: return "4Mx8x2";
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default: return "unknown";
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}
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}
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static void Show_VCMA9_Info(char *board_name, char *serial)
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{
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printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n",
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board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision());
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printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom());
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char s[50];
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int i;
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backup_t *b = (backup_t *) s;
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i = getenv_r("serial#", s, 32);
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if ((i < 0) || strncmp (s, "VCMA9", 5)) {
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get_backup_values (b);
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if (strncmp (b->signature, "MPL\0", 4) != 0) {
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puts ("### No HW ID - assuming VCMA9");
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} else {
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b->serial_name[5] = 0;
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Show_VCMA9_Info(b->serial_name, &b->serial_name[6]);
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}
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} else {
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s[5] = 0;
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Show_VCMA9_Info(s, &s[6]);
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}
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/*printf("\n");*/
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return(0);
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}
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int last_stage_init(void)
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{
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checkboard();
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stdio_print_current_devices();
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check_env();
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return 0;
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}
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/***************************************************************************
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* some helping routines
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*/
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#if !CONFIG_USB_KEYBOARD
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int overwrite_console(void)
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{
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/* return TRUE if console should be overwritten */
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return 0;
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}
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#endif
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/************************************************************************
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* Print VCMA9 Info
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************************************************************************/
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void print_vcma9_info(void)
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{
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char s[50];
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int i;
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if ((i = getenv_r("serial#", s, 32)) < 0) {
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puts ("### No HW ID - assuming VCMA9");
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printf("i %d", i*24);
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} else {
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s[5] = 0;
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Show_VCMA9_Info(s, &s[6]);
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}
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_CS8900
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rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
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#endif
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return rc;
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}
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#endif
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