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https://github.com/brain-hackers/u-boot-brain
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![Stefan Roese](/assets/img/avatar_default.png)
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
279 lines
7.2 KiB
C
279 lines
7.2 KiB
C
/*
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* (C) Copyright 2008
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* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
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*
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* Based in part on arch/powerpc/cpu/mpc8xx/scc.c.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h> /* commproc.h is included here */
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#include <malloc.h>
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#include <net.h>
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#ifdef CONFIG_KEYMILE_HDLC_ENET
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#include "../common/keymile_hdlc_enet.h"
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char keymile_slot; /* our slot number in the backplane */
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/*
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* Since, except during initialization, ethact is always HDLC ETHERNET
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* while we're in the driver, just use serial_printf() everywhere for
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* output. This avoids possible conflicts when netconsole is being
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* used.
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*/
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#define dprintf(fmt, args...) serial_printf(fmt, ##args)
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static int already_inited;
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/*
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* SCC Ethernet Tx and Rx buffer descriptors allocated at the
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* immr->udata_bd address on Dual-Port RAM
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* Provide for Double Buffering
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*/
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typedef volatile struct CommonBufferDescriptor {
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cbd_t txbd; /* Tx BD */
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cbd_t rxbd[HDLC_PKTBUFSRX]; /* Rx BD */
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} RTXBD;
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static RTXBD *rtx;
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int keymile_hdlc_enet_init(struct eth_device *, bd_t *);
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void keymile_hdlc_enet_halt(struct eth_device *);
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extern void keymile_hdlc_enet_init_bds(RTXBD *);
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extern void initCachedNumbers(int);
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/* Use SCC4 */
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#define MGS_CPM_CR_HDLC CPM_CR_CH_SCC4
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#define MGS_PROFF_HDLC PROFF_SCC4
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#define MGS_SCC_HDLC 3 /* Index, not number! */
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int keymile_hdlc_enet_init(struct eth_device *dev, bd_t *bis)
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{
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/* int i; */
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/* volatile cbd_t *bdp; */
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volatile cpm8xx_t *cp;
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volatile scc_t *sccp;
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volatile hdlc_pram_t *hpr;
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volatile iop8xx_t *iop;
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if (already_inited)
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return 0;
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cp = (cpm8xx_t *)&(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm);
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hpr = (hdlc_pram_t *)(&cp->cp_dparam[MGS_PROFF_HDLC]);
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sccp = (volatile scc_t *)(&cp->cp_scc[MGS_SCC_HDLC]);
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iop = (iop8xx_t *)&(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport);
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/*
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* Disable receive and transmit just in case.
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*/
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sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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#ifndef CONFIG_SYS_ALLOC_DPRAM
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#error "CONFIG_SYS_ALLOC_DPRAM must be defined"
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#else
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/*
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* Avoid exhausting DPRAM, which would cause a panic.
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* Actually this isn't really necessary, but leave it here
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* for safety's sake.
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*/
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if (rtx == NULL) {
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rtx = (RTXBD *) (cp->cp_dpmem +
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dpram_alloc_align(sizeof(RTXBD), 8));
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if (rtx == (RTXBD *)CPM_DP_NOSPACE)
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return -1;
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memset((void *)rtx, 0, sizeof(RTXBD));
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}
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#endif /* !CONFIG_SYS_ALLOC_DPRAM */
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/* We need the slot number for addressing. */
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keymile_slot = *(char *)(CONFIG_SYS_SLOT_ID_BASE +
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CONFIG_SYS_SLOT_ID_OFF) & CONFIG_SYS_SLOT_ID_MASK;
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/*
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* Be consistent with the Linux driver and set
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* only enetaddr[0].
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*
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* Always add 1 to the slot number so that
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* there are no problems with an ethaddr which
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* is all 0s. This should be acceptable because
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* a board should never have a slot number of 255,
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* which is the broadcast address. The HDLC addressing
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* uses only the slot number.
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*/
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dev->enetaddr[0] = keymile_slot + 1;
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#ifdef TEST_IT
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dprintf("slot %d\n", keymile_slot);
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#endif
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/* use pa8, pa9 pins for TXD4, RXD4 respectively */
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iop->iop_papar |= ((0x8000 >> 8) | (0x8000 >> 9));
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iop->iop_padir &= ~((0x8000 >> 8) | (0x8000 >> 9));
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iop->iop_paodr &= ~((0x8000 >> 8) | (0x8000 >> 9));
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/* also use pa0 as CLK8 */
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iop->iop_papar |= 0x8000;
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iop->iop_padir &= ~0x8000;
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iop->iop_paodr &= ~0x8000;
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/* use pc5 as CTS4 */
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iop->iop_pcpar &= ~(0x8000 >> 5);
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iop->iop_pcdir &= ~(0x8000 >> 5);
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iop->iop_pcso |= (0x8000 >> 5);
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/*
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* SI clock routing
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* use CLK8
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* this also connects SCC4 to NMSI
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*/
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cp->cp_sicr = (cp->cp_sicr & ~0xff000000) | 0x3f000000;
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/* keymile_rxIdx = 0; */
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/*
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* Initialize function code registers for big-endian.
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*/
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hpr->rfcr = SCC_EB;
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hpr->tfcr = SCC_EB;
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/*
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* Set maximum bytes per receive buffer.
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*/
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hpr->mrblr = MAX_FRAME_LENGTH;
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/* Setup CRC generator values for HDLC */
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hpr->c_mask = 0x0000F0B8;
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hpr->c_pres = 0x0000FFFF;
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/* Initialize all error counters to 0 */
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hpr->disfc = 0;
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hpr->crcec = 0;
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hpr->abtsc = 0;
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hpr->nmarc = 0;
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hpr->retrc = 0;
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/* Set maximum frame length size */
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hpr->mflr = MAX_FRAME_LENGTH;
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/* set to 1 for per frame processing change later if needed */
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hpr->rfthr = 1;
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hpr->hmask = 0xff;
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hpr->haddr2 = SET_HDLC_UUA(keymile_slot);
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hpr->haddr3 = hpr->haddr2;
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hpr->haddr4 = hpr->haddr2;
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/* broadcast */
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hpr->haddr1 = HDLC_BCAST;
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hpr->rbase = (unsigned int) &rtx->rxbd[0];
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hpr->tbase = (unsigned int) &rtx->txbd;
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#if 0
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/*
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* Initialize the buffer descriptors.
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*/
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bdp = &rtx->txbd;
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bdp->cbd_sc = 0;
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bdp->cbd_bufaddr = 0;
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bdp->cbd_sc = BD_SC_WRAP;
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/*
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* Setup RX packet buffers, aligned correctly.
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* Borrowed from net/net.c.
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*/
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MyRxPackets[0] = &MyPktBuf[0] + (PKTALIGN - 1);
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MyRxPackets[0] -= (ulong)MyRxPackets[0] % PKTALIGN;
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for (i = 1; i < HDLC_PKTBUFSRX; i++)
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MyRxPackets[i] = MyRxPackets[0] + i * PKT_MAXBLR_SIZE;
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bdp = &rtx->rxbd[0];
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for (i = 0; i < HDLC_PKTBUFSRX; i++) {
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bdp->cbd_sc = BD_SC_EMPTY;
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/* Leave space at the start for INET header. */
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bdp->cbd_bufaddr = (unsigned int)(MyRxPackets[i] +
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INET_HDR_ALIGN);
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bdp++;
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}
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bdp--;
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bdp->cbd_sc |= BD_SC_WRAP;
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#else
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keymile_hdlc_enet_init_bds(rtx);
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#endif
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/* Let's re-initialize the channel now. We have to do it later
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* than the manual describes because we have just now finished
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* the BD initialization.
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*/
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cp->cp_cpcr = mk_cr_cmd(MGS_CPM_CR_HDLC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG);
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sccp->scc_gsmrl = SCC_GSMRL_MODE_HDLC;
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/* CTSS=1 */
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sccp->scc_gsmrh = SCC_GSMRH_CTSS;
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/* NOF=0, RTE=1, DRT=0, BUS=1 */
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sccp->scc_psmr = ((0x8000 >> 6) | (0x8000 >> 10));
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/* loopback for local testing */
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#ifdef GJTEST
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dprintf("LOOPBACK!\n");
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sccp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
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#endif
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/*
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* Disable all interrupts and clear all pending
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* events.
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*/
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sccp->scc_sccm = 0;
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sccp->scc_scce = 0xffff;
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/*
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* And last, enable the transmit and receive processing.
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*/
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sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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dprintf("%s: HDLC ENET Version 0.3 on SCC%d\n", dev->name,
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MGS_SCC_HDLC + 1);
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/*
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* We may not get an ARP packet because ARP was already done on
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* a different interface, so initialize the cached values now.
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*/
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initCachedNumbers(1);
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already_inited = 1;
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return 0;
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}
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void keymile_hdlc_enet_halt(struct eth_device *dev)
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{
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#if 0 /* just return, but keep this for reference */
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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/* maybe should do a graceful stop here? */
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immr->im_cpm.cp_scc[MGS_SCC_HDLC].scc_gsmrl &=
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~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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#endif
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}
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#endif /* CONFIG_KEYMILE_HDLC_ENET */
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