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https://github.com/brain-hackers/u-boot-brain
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![Stefan Roese](/assets/img/avatar_default.png)
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
240 lines
6.6 KiB
C
240 lines
6.6 KiB
C
/*
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* (C) Copyright 2005
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* John Otken, jotken@softadvances.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/ppc4xx-isram.h>
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#include <spd_sdram.h>
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#include "epld.h"
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*************************************************************************
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* int board_early_init_f()
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*
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************************************************************************/
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int board_early_init_f(void)
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{
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u32 mfr;
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mtebc( PB0AP, 0x03800000 ); /* set chip selects */
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mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
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mtebc( PB1AP, 0x03800000 );
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mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
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mtebc( PB2AP, 0x03800000 );
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mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
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mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */
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mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */
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mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */
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mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */
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mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */
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mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
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mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */
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mtdcr( UIC1SR, 0xffffffff );
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mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */
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mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */
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mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */
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mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */
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mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */
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mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
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mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */
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mtdcr( UIC0SR, 0xffffffff );
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mfsdr(SDR0_MFR, mfr);
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mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
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mtsdr(SDR0_MFR, mfr);
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return 0;
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}
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/*************************************************************************
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* int misc_init_r()
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*
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************************************************************************/
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int misc_init_r(void)
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{
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volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
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/* set modes of operation */
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x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
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EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
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/* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
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x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
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/* put Ethernet+PHY in reset */
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x->ethuart &= ~EPLD2_RESET_ETH_N;
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udelay(10000);
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/* take Ethernet+PHY out of reset */
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x->ethuart |= EPLD2_RESET_ETH_N;
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return 0;
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}
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/*************************************************************************
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* int checkboard()
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*
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************************************************************************/
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int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: Luan - AMCC PPC440SP Evaluation Board");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return 0;
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}
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/*
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* Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
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* board specific values.
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*/
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u32 ddr_clktr(u32 default_val) {
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return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
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}
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/*************************************************************************
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* hw_watchdog_reset
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*
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* This routine is called to reset (keep alive) the watchdog timer
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*
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************************************************************************/
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#if defined(CONFIG_HW_WATCHDOG)
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void hw_watchdog_reset(void)
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{
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}
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#endif
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/*************************************************************************
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* int on_off()
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*
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************************************************************************/
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static int on_off( const char *s )
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{
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if (strcmp(s, "on") == 0) {
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return 1;
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} else if (strcmp(s, "off") == 0) {
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return 0;
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}
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return -1;
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}
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/*************************************************************************
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* void l2cache_disable()
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*
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************************************************************************/
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static void l2cache_disable(void)
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{
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mtdcr( L2_CACHE_CFG, 0 );
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}
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/*************************************************************************
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* void l2cache_enable()
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*
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************************************************************************/
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static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
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{
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mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
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mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */
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mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
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while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */
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mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
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mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
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mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */
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mtdcr( L2_CACHE_SNP1, 0 );
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__asm__ volatile ("sync"); /* msync */
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mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */
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__asm__ volatile ("sync");
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}
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/*************************************************************************
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* int l2cache_status()
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*
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************************************************************************/
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static int l2cache_status(void)
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{
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return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
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}
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/*************************************************************************
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* int do_l2cache()
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*
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************************************************************************/
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int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
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{
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switch (argc) {
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case 2: /* on / off */
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switch (on_off(argv[1])) {
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case 0: l2cache_disable();
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break;
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case 1: l2cache_enable();
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break;
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}
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/* FALL TROUGH */
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case 1: /* get status */
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printf ("L2 Cache is %s\n",
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l2cache_status() ? "ON" : "OFF");
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return 0;
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default:
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cmd_usage(cmdtp);
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return 1;
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}
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return 0;
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}
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U_BOOT_CMD(
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l2cache, 2, 1, do_l2cache,
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"enable or disable L2 cache",
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"[on, off]\n"
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" - enable or disable L2 cache"
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);
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